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Programmable Gain Amplifier (programmable + gain_amplifier)

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Engineering100%

Selected Abstracts

A switched-capacitor programmable gain amplifier using dynamic element matching

IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 6 2007
Jun Wang Non-member
Abstract This paper discusses the effect of capacitor mismatch errors on gain accuracy of switched-capacitor programmable gain amplifier (SC PGA). To improve gain deviations caused by mismatch errors, the dynamic element matching (DEM) algorithm is applied to the SC PGA circuits. It uses digital gain-control signal to dynamically vary the matched capacitor combinations so that the effective capacitances of the sampling and feedback capacitor arrays are averaged, and thus the gain deviations due to capacitor mismatch errors are eliminated to a significant extent. The distortion caused by mismatch errors shift to certain frequency bands, and could be reduced or removed by subsequent processing such as lowpass filtering. A 4-bit SC PGA using DEM was designed in 0.25 µm CMOS process with 2.5 V voltage supply, including offset cancellation and clock bootstrapped circuits operating at a sampling frequency of 10 MHz. Test results have indicated that gain deviations due to mismatch errors are substantially reduced. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source]

Using MOS current dividers for linearization of programmable gain amplifiers

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 4 2008
M. Teresa Sanz
Abstract Two highly linear, digitally programmable gain amplifiers are presented and compared in terms of linearity, frequency, area and power consumption. High linearity and wide gain tuning range with moderate area consumption are the main benefits of both configurations. Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three-bit prototypes were integrated in a 0.35,µm,3.3,V CMOS process with 2.5,V supply voltage. Experimental distortion levels are better than ,68,dB for 1,MHz and 1,Vp,p output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown. Copyright © 2007 John Wiley & Sons, Ltd. [source]