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Nm CMOS Technology (nm + cmo_technology)

Distribution by Scientific Domains
Engineering100%

Selected Abstracts

A scalable advanced RF IC design-oriented MOSFET model,

INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 4 2008
Matthias Bucher
Abstract This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The scaling behaviour over a large range of channel lengths and bias conditions is presented. Long-channel devices show significant non-quasi static effects while in short-channel devices the parasitics modelling is critical. This is illustrated with Y-parameters and ft vs. ID in NMOS and PMOS devices, showing good overall RF modelling abilities of the EKV3 MOSFET model. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008. [source]

A 60-GHz low-noise amplifier for 60-GHz dual-conversion receiver

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2009
Yo-Sheng Lin
Abstract A 60-GHz-band low-noise amplifier (LNA) using bulk 65-nm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascade common-source stages followed by a cascode output stage. Current-sharing technique is adopted in the second and third stage to reduce power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain over the 57,64-GHz-band of interest. This LNA achieved input return loss (S11) of ,10.6 to ,37.4 dB, voltage gain (AV) of 10.7,18.8 dB, reverse isolation (S12) of ,43.5 to ,48.1 dB, input referred 1-dB compression point (P1dB-in) of ,16.2 to ,20.8 dBm, and input third-order intermodulation point (IIP3) of ,4 to ,7.5 dBm over the 57,64-GHz-band of interest. It consumed only a small DC power of 21.4 mW. In addition, the chip area was only 0.849 × 0.56 mm2, including all the test pads and bypass capacitors. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 885,891, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24200 [source]

A low power low noise amplifier with subthreshold operation in 130 nm CMOS technology

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 11 2008
Ickhyun Song
Abstract In this article, a 5.8 GHz ISM-band CMOS low noise amplifier (LNA) operating in a subthreshold region is presented. A conventional source degeneration inductor is eliminated for higher signal gain while providing reasonable input impedance. The LNA is fabricated using 130 nm CMOS technology and measured signal gain, noise figure, and power consumption are 13.4 dB, 5.2 dB, and 980 ,W, respectively, at target frequency. Also the LNA achieves the highest figure of merit among the recently published subthreshold LNAs. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2762,2764, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23788 [source]