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Low-noise Amplifier (low-noise + amplifier)

Distribution by Scientific Domains

Engineering	100%

Distribution within Engineering

Communication Technology	90%
General & Introductory Electrical & Electronics Engineering	10%

Selected Abstracts

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS, Issue 5 2009
M. S. Alam
Abstract The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source,drain extension, which simultaneously improves maximum frequency of oscillation ,max because of lower gate to drain capacitance, and intrinsic gain AV0,=,gm/gds, due to lower output conductance gds. The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current Id on drain,source Vds and gate,source Vgs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (Jds,10,µA/µm) improvement was observed in both third-order-intercept IIP3 (,10,dBm) and intrinsic gain AV0 (,20,dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of Id with respect to gate voltage and lower gds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd. [source]

A reconfigurable DCS1800/W-CDMA LNA: Design and implementation issues

INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 1 2009
Cristian Pavão Moreira
Abstract The authors present in this article a dual-standard dual-mode low-noise amplifier (LNA) for DCS1800/W-CDMA-FDD applications. To save die area compared to conventional parallel LNAs, the authors have employed an alternative circuit configuration. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. The LNA die area is 1.0 × 1.2 mm2 and it consumes 6.8 mW (3.8 mA under 1.8 V), including bias circuitry. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [source]

Alternative approach to low-noise amplifier design for ultra-wideband applications

INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 2 2007
Qiang Li
Abstract Conventional ultra-wideband low-noise amplifiers require a flat gain over the entire 3.1,10.6 GHz bandwidth, which severely restraints the trade-off spaces in low noise amplifier design. This article proposes a relaxed gain-flatness requirement based on system level investigations. Considering the wireless transceiver front-end with antenna and propagation channel, the unflat-gain low-noise amplifier with an incremental gain characteristic does not degrade the performance of overall system. As an alternative to its flat-gain counterpart, the proposed unflat gain requirement tolerates gain ripple as large as 10 dB, which greatly eases the design challenges to low-noise amplifier for ultra-wideband wireless receivers. Two low-noise amplifier examples are given to demonstrate the feasibility and design flexibility under the proposed gain-flatness requirement. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007. [source]

Analysis and design of a fully integrated CMOS low-noise amplifier for concurrent dual-band receivers

INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 5 2006
Y. P. Zhang
Abstract This article thoroughly analyzes a concurrent dual-band low-noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual-band LNA. As an example of the analysis, a fully integrated dual-band LNA is designed in a standard 0.18-,m 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high-band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5-V supply voltage and achieves voltage gains of 14 and 22 dB, input S11 of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006. [source]

A 60-GHz CMOS receiver front-end with integrated 180° out-of-phase Wilkinson power divider

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 12 2010
Jen-How Lee
Abstract A 60-GHz receiver front-end with an integrated 180° out-of-phase Wilkinson power divider using standard 0.13 ,m CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA) with 12.4-dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180° out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input return loss at RF port better than ,10 dB for frequencies from 52.3 to 62.3 GHz. At IF of 20 MHz, the receiver front-end achieved maximum conversion gain of 18.7 dB at RF of 56 GHz. The corresponding 3-dB bandwidth (,3 dB) of RF is 9.8 GHz (50.8,60.6 GHz). The measured minimum noise figure (NF) was 9 dB at 58 GHz, an excellent result for a 60-GHz-band CMOS receiver front-end. In addition, the measured input 1-dB compression point (P1 dB) and input third-order inter-modulation point (IIP3) are ,20.8 dBm and ,12 dBm, respectively, at 60 GHz. These results demonstrate the adopted receiver front-end architecture is very promising for high-performance 60-GHz-band RFIC applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2688,2694, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25559 [source]

A novel CMOS distributed receiver front-end for wireless ultrawideband receivers

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2010
Xin Guan
Abstract An ultrawideband CMOS distributed receiver front-end utilizing cascade gain cell structure is designed in Jazz 0.18-,m CMOS process. The proposed distributed front-end, fully integrating a low-noise amplifier (LNA) and mixer together, demonstrates 11.5,14 dB gain, 5,6.5 dB noise figure and more than 9-dB RF/LO return loss over 2,17 GHz with a fixed IF frequency of 500 MHz and LO power of 5 dBm. The entire circuit occupies 1.7 × 1.0 mm2 including on-wafer pads and consumes 170 mA from 1.8-V voltage supply. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1790,1792, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25316 [source]

A 60-GHz low-noise amplifier for 60-GHz dual-conversion receiver

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2009
Yo-Sheng Lin
Abstract A 60-GHz-band low-noise amplifier (LNA) using bulk 65-nm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascade common-source stages followed by a cascode output stage. Current-sharing technique is adopted in the second and third stage to reduce power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain over the 57,64-GHz-band of interest. This LNA achieved input return loss (S11) of ,10.6 to ,37.4 dB, voltage gain (AV) of 10.7,18.8 dB, reverse isolation (S12) of ,43.5 to ,48.1 dB, input referred 1-dB compression point (P1dB-in) of ,16.2 to ,20.8 dBm, and input third-order intermodulation point (IIP3) of ,4 to ,7.5 dBm over the 57,64-GHz-band of interest. It consumed only a small DC power of 21.4 mW. In addition, the chip area was only 0.849 × 0.56 mm2, including all the test pads and bypass capacitors. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 885,891, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24200 [source]

A 5.79-dB NF, 30-GHz-band monolithic LNA with 10 mW power consumption in standard 0.18-,m CMOS technology

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2009
Chi-Chen Chen
Abstract A 30-GHz (Ka-band) low-noise amplifier (LNA) with 10 mW power consumption (PDC) using standard 0.18-,m CMOS technology was designed and implemented. To achieve sufficient gain, this LNA was composed of three cascade common-source stages, and a series peaking inductor (Lg3) was added to the input terminal of the third stage to boost the peak gain (S21-max) from 11.7 (at 28.8 GHz) to 14.5 (at 28 GHz), i.e., 23.9% (simulation). Shunt RC feedback was adopted in the third stage for achieving good output impedance matching. At 30 GHz, this LNA achieved excellent input return loss (S11) of ,19.5 dB, output return loss (S22) of ,23.8 dB, forward gain (S21) of 11.1 dB, reverse isolation (S12) of ,49.2 dB, and noise figure of 5.79 dB. The corresponding gain/PDC was 1.11, which is better than those of the CMOS LNAs around 30 GHz reported in the literature. The measured input-referred 1-dB compression point (P1dB-in) and input third-order intermodulation point (IIP3) were ,10.9 and ,2 dBm, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 933,937, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24250 [source]

A low-power V-band CMOS low-noise amplifier using current-sharing technique

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 7 2008
Hong-Yu Yang
Abstract A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 ,m CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and four stages to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (AV) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1dB-in) of ,20 dBm, and input third-order inter-modulation point (IIP3) of ,9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91 × 0.58 mm2, including all the test pads and bypass capacitors. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1876,1879, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23523 [source]

A high-performance wideband cmos low-noise amplifier using inductive series and parallel peaking techniques

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 5 2008
Jen-How Lee
Abstract A 1,11 GHz wideband low-noise amplifier (LNA) with good phase linearity properties (group-delay variation is only ±35.56 ps across the 3.1,10.6 GHz band of interest) using standard 0.18 ,m CMOS technology is reported. To enhance the bandwidth for achieving both high and flat gain and small group-delay variation, the inductive shunt-peaking technique is adopted in the load of the input stage, while the inductive series-peaking technique is adopted in the input terminal of the output stage. The wideband LNA dissipates 29.46 mW power and achieves input return loss (S11) of ,9.32 to ,9.98 dB, flat forward gain (S21) of 11 ± 1 dB, reverse isolation (S12) of ,46 to ,60 dB, and noise figure of 4.15,4.85 dB over the 3.1,10.6 GHz band of interest. Good 1-dB compression point (P1 dB) of ,14 dBm and input third-order inter-modulation point (IIP3) of ,3 dBm are achieved at 6.4 GHz. The chip area is only 675 ,m × 632 ,m excluding the test pads. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1240,1244, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23338 [source]

Distributed power amplifier/feedback low noise amplifier switch-less front-end

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2006
Shaoyong Zheng
Abstract Distributed amplifiers are used as a one-way amplifier, with two ports terminated and unused. A new topology that places a feedback low-noise amplifier at one of these unused ports is presented, which can be used as a TDD/TDMA RF front end, negating the need for a switch. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1659,1662, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21690 [source]

A monolithic 1.57/5.25-GHz concurrent dual-band low-noise amplifier using InGaP/GaAs HBT technology

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 1 2004
Shey-Shi Lu
Abstract A monolithic concurrent dual-band low-noise amplifier (LNA) using InGaP/GaAs HBT technology is demonstrated for the first time. The LNA provides narrowband gain and matching simultaneously at both 1.57-GHz (GPS) and 5.25-GHz (ISM) bands. It consumes only 15-mW power and achieves transducer gains (S21) of 25.3 and 14.3 dB, input return losses (S11) of 6.8 and 11.5 dB, reverse isolation (S12) of ,30.8 and ,32.2 dB, and noise figures of 2.55 and 4.5 dB at these two bands, respectively. The performance at 5.25 GHz is comparable with the 2.45/5.25-GHz concurrent dual-band CMOS LNA with a bonding wire as the gate inductor using 0.35-m CMOS technology 1. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 58,60, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20206 [source]

Low-Noise Fully Differential Amplifiers Using JFET-CMOS Integration Technology for Smart Sensors

IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 3 2008
Hidekuni Takao Member
Abstract In this paper, CMOS-based low-noise amplifiers with JFET-CMOS technology for high-resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front-end circuit in many sensor applications. Low-noise JFET devices are used as input pair of the input differential stages or source-grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET-CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET-CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise-reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about , 18 dB at 2.5 Hz. JFET-CMOS technology is very effective in improving the signal-to-noise ratio (SNR) of a sensor interface circuit with CMOS-based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source]