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Hardware Implementation (hardware + implementation)
Selected AbstractsHardware implementation of CNN architecture-based test bed for studying synchronization phenomenon in oscillatory and chaotic networksINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 4 2009Ákos Tar Abstract A 3D modular cellular nonlinear network (CNN) architecture-based test bed, with four-neighbor connectivity, used to study synchronization phenomena in oscillatory and chaotic networks is designed. The architecture is implemented as hardware panels including a standalone robust Chua's circuit kit. The details of electronic implementation along with several test cases of connecting Chua's circuits in different topologies are provided. Test cases are adequately supported by oscilloscope traces. Copyright © 2008 John Wiley & Sons, Ltd. [source] Hardware-Based Volumetric Knit-WearCOMPUTER GRAPHICS FORUM, Issue 3 2002Katja Daubert We present a hardware-based, volumetric approach for rendering knit wear at very interactive rates. A single stitch is represented by a volumetric texture with each voxel storing the main direction of the strands of yarn inside it. We render the knit wear in layers using an approximation of the Banks model. Our hardware implementation allows specular and diffuse material properties to change from one voxel to the next. This enables us to represent yarn made up of different components or render garments with complicated color patterns. Furthermore, our approach can handle self-shadowing of the stitches, and can easily be adapted to also include view-independent scattering. The resulting shader lends itself naturally to mip-mapping, and requires no reordering of the base geometry, making it versatile and easy to use. Categories and Subject Descriptors (according to ACM CCS): I.3.3 [Computer Graphics]: Hardware Applications Volumetric Textures [source] Using parallelization and hardware concurrency to improve the performance of a genetic algorithmCONCURRENCY AND COMPUTATION: PRACTICE & EXPERIENCE, Issue 4 2007Vijay Tirumalai Abstract Genetic algorithms (GAs) are powerful tools for solving many problems requiring the search of a solution space having both local and global optima. The main drawback for GAs is the long execution time normally required for convergence to a solution. This paper discusses three different techniques that can be applied to GAs to improve overall execution time. A serial software implementation of a GA designed to solve a task scheduling problem is used as the basis for this research. The execution time of this implementation is then improved by exploiting the natural parallelism present in the algorithm using a multiprocessor. Additional performance improvements are provided by implementing the original serial software GA in dedicated reconfigurable hardware using a pipelined architecture. Finally, an advanced hardware implementation is presented in which both pipelining and duplicated hardware modules are used to provide additional concurrency leading to further performance improvements. Copyright © 2006 John Wiley & Sons, Ltd. [source] Real-time signal processing for high-density microelectrode array systemsINTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, Issue 11 2009K. Imfeld Abstract The microelectrode array (MEA) technology is continuously progressing towards higher integration of an increasing number of electrodes. The ensuing data streams that can be of several hundreds or thousands of Megabits/s require the implementation of new signal processing and data handling methodologies to substitute the currently used off-line analysis methods. Here, we present one approach based on the hardware implementation of a wavelet-based solution for real-time processing of extracellular neuronal signals acquired on high-density MEAs. We demonstrate that simple mathematical operations on the discrete wavelet transform (DWT) coefficients can be used for efficient neuronal spike detection and sorting. As the DWT is particularly well suited for implementation on dedicated hardware, we elaborated a wavelet processor on a field programmable gate array (FPGA) in order to compute the wavelet coefficients on 256 channels in real-time. By providing sufficient hardware resources, this solution can be easily scaled up for processing more electrode channels. Copyright © 2008 John Wiley & Sons, Ltd. [source] A configuration for realizing floating, linear, voltage-controlled resistance, inductance and FDNC elementsINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 5 2009R. Senani Abstract A configuration using current feedback amplifiers has been presented, which is capable of realizing linear, positive/negative voltage-controlled resistance, voltage-controlled inductance and voltage-controlled frequency-dependent negative conductance in floating form (and thereby, also in grounded form) from the same structure. The workability of the proposed configuration has been demonstrated by hardware implementation results using AD 844-type current feedback op-amps (CFOAs) and BFW-11-type JFETs and the workability in high-frequency range has been demonstrated by SPICE simulation using CMOS CFOAs. Copyright © 2008 John Wiley & Sons, Ltd. [source] Hyperchaotic signal generation via DSP for efficient perturbations to liquid mixingINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 1 2009Zhong Zhang Abstract This paper presents the design, simulation, hardware implementation and an application in liquid mixing of some hyperchaotic circuits, based on the digital signal processing (DSP) technology. The hyperchaotic Chen's system is used as an example to show the system discretization and variable renormalization in the design process. Numerical simulation is given to verify the hardware signal generator. The implemented hardware of Chen's system generates outputs in good agreement with the numerical simulation. The hyperchaotic signal output from the DSP is applied to generate complex perturbations in liquid mixing experiments. Dye dispersion experiments show that the induced hyperchaotic motion effectively helps enhance the mixing homogeneity in the stirred-tank-based mixer in our laboratory. Copyright © 2008 John Wiley & Sons, Ltd. [source] Analog-VLSI, array-processor-based, Bayesian, multi-scale optical flow estimationINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 1 2006L. Török Abstract Optical flow (OF) estimation aims at derive a motion-vector field that characterizes motions on a video sequence of images. In this paper, we propose a new multi-scale (or scale-space) algorithm that generates OF on cellular neural/non-linear network universal machine, a general purpose analog-VLSI hardware, at resolution of 128 × 128 with fair accuracy and working over a speed of 100 frames/s. The performance of the hardware implementation of the proposed algorithm is measured on a standard image sequence. As far as we are concerned, this is the first time when an OF estimator hardware is tested on a practical-size standard image sequence. Copyright © 2006 John Wiley & Sons, Ltd. [source] | |||||||||||||