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Gate Leakage Current (gate + leakage_current)
Selected AbstractsInvestigation of multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) sub-50,nm MOSFET: A novel designINTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS, Issue 3 2009Rishu Chaujar Abstract In this paper, a two-dimensional (2D) analytical sub-threshold model for a novel sub-50,nm multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO2 -based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain-induced barrier lowering, sub-threshold drain current and sub-threshold swing. Results reveal that MLGEWE-RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high-speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd. [source] Optimization of the ohmic contact processing in InAlN//GaN high electron mobility transistors for lower temperature of annealingPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 1 2010Karol Abstract In this article, we optimized the ohmic contact processing in InAlN/GaN high electron mobility transistors for the lower temperature of annealing by recessing of metalliza-tion to approach the 2DEG at the InAlN/GaN interface. The ohmic contacts which were recessed down to 5 nm depth and annealed at 700 °C 2 min. exhibited the contact resistance of 0,39 ,mm while the channel sheet resistance was 210 ,/square. These values are comparative to values of contacts processed at more conventional an-nealing conditions (800 °C, 2 min). Moreover we applied the recessed ohmic contact technology to fabricate Schottky barrier (SB) HEMTs and MOSHEMTs with Al2O3 dielectric film. For MOSHEMTs, we measured the maximal reduction of the gate leakage current by about 6 orders of magnitude if compared with SB HEMTs. The maximal drain current of MOSHEMTs was about 750 mA/mm at VGS = 0 V and the maximal extrinsic transconductance (gme) reached 101 mS/mm. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Tunneling current in gate dielectric stack in sub-45 nanometer CMOS devicesPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 12 2009Hitender Kumar Tyagi Abstract Direct tunneling current through dual layer SiO2/high-K dielectric structures are investigated for substrate injection. Correlation of dielectric constants and band offsets with respect to silicon has been taken into consideration in order to identify possible materials to construct these devices. The direct tunneling current in oxide/high-K dielectric structures with equivalent oxide thickness (EOT) of 2.0 nm can be significantly lower than that through single layer oxides of the same thickness. Various structures and materials of high-K stacks of interest have been examined and compared to access the reduction of gate current in these structures. It is estimated that HfO2/SiO2 dual stack structure can reduce gate leakage current by four orders of magnitude as compared with pure SiO2 layer of same EOT. The importance of interfacial layer in dual stack structure is high-lighted for the reduction of gate leakage current. The present approach is capable of modeling high-K stack structures consisting of multiple layers of different dielectrics (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Influence of barrier thickness on AlInN/AlN/GaN heterostructures and device propertiesPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue S2 2009H. Behmenburg Abstract We report on structural and device properties of AlInN/AlN/GaN transistor heterostructures grown by metal organic vapour phase epitaxy (MOVPE) on 2, sapphire substrates with AlInN barriers of thicknesses between 4 nm and 10 nm. The In content and thickness of the thin AlInN barrier is shown to be well determinable by high-resolution X-ray diffraction (HRXRD). Room temperature Hall measurements yielded similar mobility between 1400 cm2V,1s,1 and 1520 cm2V,1s,1 on all samples and increasing sheet carrier concentration ns with rising barrier thickness resulting in a minimum sheet resistance value of 200 Ohm/,. The effect of surface passivation with Si3N4 on the electrical properties is investigated and found to strongly increase sheet carrier concentration ns of the two-dimensional electron gas (2DEG) to values above 2×1013cm,2. Characterization of transistors with gate length Lg of 1.5 ,m produced from the grown samples reveals high transconductance (gm) and a maximum drain current (ID) of 300 mS/mm and ,1 A/mm, respectively. For the sample with 4.6 nm barrier thickness, a reduced gate leakage current (IGL) and a absolute value of the threshold voltage (Vth) of -1.2 V is detected. Radio frequency (RF) measurements of passivated samples lead to maximum current gain cut-off frequencies ft of 11 GHz and maximum oscillating frequencies fmax of 25 GHz. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Phonon-electric effect in nano-scale transistorsPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 8 2005D. W. Horsell Abstract A novel dc current is shown to exist in a nano-scale transistor structure. This current is accounted for by a non-equilibrium distribution of electrons generated by hot electrons from the gate. It is shown that by this mechanism the gate leakage current can be substantially magnified. It is this, along with the asymmetry inherent to the mesoscopic system, that can maintain a dc current flow across the channel. We realize this current experimentally and show that it may dominate other currents present in the system. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Impact of native oxides beneath the gate contact of AlGaN/GaN HFET devicesPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 7 2005D. Mistele Abstract We report on the decisive role of oxides at the surface of AlGaN/GaN Heterostructure Field Effect Transistors (HFETs). The effect of oxides at the surface is twofold, on one hand the 2DEG in the channel is directly influenced by surface charges and surface potential correlated to surface oxides (D. Mistele et al., phys. stat. sol. (a) 194 (2), 452 (2002). [1]), on the other hand, a surface oxide below a subsequently deposited gate contact increases the barrier height and therefore reduces leakage currents by several orders of magnitude. This study includes various surface treatments on AlGaN/GaN heterostructures such as etching by HCl, oxidation by O2 -plasma, and subsequent passivation by Si3N4. Next, we report on the correlation between gate leakage current and the drain current and dedicate this behavior to the Schottky barrier and to surface related charging effects. A model with the surface related charging effects on the 2DEG and the barrier height is discussed. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Fabrication of AlGaN/GaN MIS-HFET using an Al2O3 high k dielectricPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 7 2003Ki-Yeol Park Abstract We report on a metal,insulator,semiconductor AlGaN/GaN heterostructure field-effect transistor (MIS-HFET) using Al2O3 simultaneously for channel passivation layer and as a gate insulator which was deposited by plasma enhanced atomic layer deposition(PE-ALD). Capacitance,voltage measurements show successful surface passivation by the Al2O3 dielectric layer. For a gate length 1.2 ,m with 15 ,m source-to-drain spacing the maximum drain current was 1.22 A/mm, the maximum transconductance was 166 mS/mm and the gate leakage current was 4 nA/mm at Vgs = ,20 V which is at least three orders of magnitude lower than that of conventional AlGaN/GaN HFETs. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Low interface state density AlGaN/GaN MOSHFETs with photochemical vapor deposition SiO2 layersPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 7 2003C. K. Wang Abstract High quality SiO2 was successfully deposited onto AlGaN by photo chemical vapor deposition (photo-CVD) using D2 lamp as the excitation source. It was found that the interface state density was only 1.1 × 1011 cm,2 eV,1. AlGaN/GaN metal,oxide,semiconductor heterojunction field effect transistors (MOSHFETs) were also fabricated with such photo-CVD oxide as the insulating layer. Compared with AlGaN/GaN metal,semiconductor HFETs (MESHFETs) with similar structure, it was found that we could reduce the gate leakage current by more than four orders of magnitude by inserting the 32 nm-thick photo-CVD SiO2 layer between AlGaN/GaN and gate metal. With a 1 ,m gate length, it was found that room temperature saturated Ids, maximum gm and gate voltage swing (GVS) of the fabricated nitride-based MOSHFET are 800 mA/mm, 86 mS/mm and 9 V, respectively. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Fully Transparent Non-volatile Memory Thin-Film Transistors Using an Organic Ferroelectric and Oxide Semiconductor Below 200,°CADVANCED FUNCTIONAL MATERIALS, Issue 6 2010Sung-Min Yoon Abstract A fully transparent non-volatile memory thin-film transistor (T-MTFT) is demonstrated. The gate stack is composed of organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and oxide semiconducting Al-Zn-Sn-O (AZTO) layers, in which thin Al2O3 is introduced between two layers. All the fabrication processes are performed below 200,°C on the glass substrate. The transmittance of the fabricated device was more than 90% at the wavelength of 550,nm. The memory window obtained in the T-MTFT was 7.5,V with a gate voltage sweep of ,10 to 10,V, and it was still 1.8,V even with a lower voltage sweep of ,6 to 6,V. The field-effect mobility, subthreshold swing, on/off ratio, and gate leakage currents were obtained to be 32.2,cm2 V,1 s,1, 0.45,V decade,1, 108, and 10,13 A, respectively. All these characteristics correspond to the best performances among all types of non-volatile memory transistors reported so far, although the programming speed and retention time should be more improved. [source] Molecular Self-Assembled Monolayers and Multilayers for Organic and Unconventional Inorganic Thin-Film Transistor ApplicationsADVANCED MATERIALS, Issue 14-15 2009Sara A. DiBenedetto Abstract Principal goals in organic thin-film transistor (OTFT) gate dielectric research include achieving: (i) low gate leakage currents and good chemical/thermal stability, (ii) minimized interface trap state densities to maximize charge transport efficiency, (iii) compatibility with both p- and n- channel organic semiconductors, (iv) enhanced capacitance to lower OTFT operating voltages, and (v) efficient fabrication via solution-phase processing methods. In this Review, we focus on a prominent class of alternative gate dielectric materials: self-assembled monolayers (SAMs) and multilayers (SAMTs) of organic molecules having good insulating properties and large capacitance values, requisite properties for addressing these challenges. We first describe the formation and properties of SAMs on various surfaces (metals and oxides), followed by a discussion of fundamental factors governing charge transport through SAMs. The last section focuses on the roles that SAMs and SAMTs play in OTFTs, such as surface treatments, gate dielectrics, and finally as the semiconductor layer in ultra-thin OTFTs. [source] Strain-engineered novel III,N electronic devices with high quality dielectric/semiconductor interfacesPHYSICA STATUS SOLIDI (A) APPLICATIONS AND MATERIALS SCIENCE, Issue 1 2003M. Asif Khan Abstract Since the early demonstration of 2D-electron gas [M. A. Khan et al., Appl. Phys. Lett. 60, 3027 (1992)] and a heterojunction field effect transistor (HFET) [M. Asif Khan et al., Appl. Phys. Lett. 63, 1214 (1993)] in III,N materials, rapid progress has been made to improve the DC and RF performance of GaN,AlGaN based HFETs. Stable and impressive microwave powers as high as 4,8 W/mm have been reported for device operation frequencies from 10 to 35 GHz. The key reason for these high performance numbers is an extremely large sheet carrier densities (>1 × 1013 cm,2) that can be induced at the interfaces in III,N hetereojunction [A. Bykhovsk et al., J. Appl. Phys. 74, 6734 (1993); M. Asif Khan et al., Appl. Phys. Lett. 75, 2806 (1999)]. These are instrumental in screening the channel dislocations thereby retaining large room temperature carrier mobilities (>1500 cm2/Vs) and sheet resistance as low as 300 ,/sq. These numbers and the high breakdown voltages of the large bandgap III,N material system thus enable rf-power approximately 5,10 times of that possible with GaAs and other competitor's technologies. We have recently introduced a unique pulsed atomic layer epitaxy approach to deposit AlN buffer layers and AlN/AlGaN superlattices [J. Zhang et al., Appl. Phys. Lett. 79, 925 (2001); J. P. Zhang et al., Appl. Phys. Lett. 80, 3542 (2002)] to manage strain and decrease the dislocation densities in high Al-content III,N layers. This has enabled us to significantly improve GaN/AlGaN hetereojunctions and the device isolation. The resulting low defect layers are not only key to improving the electronic but also deep ultraviolet light-emitting diode devices. For deep UV LED's they enabled us to obtain peak optical powers as high as 10 mW and 3 mW for wavelengths as short as 320 nm and 278 nm. Building on our past work [M. Asif Khan et al., Appl. Phys. Lett. 77, 1339 (2000); X. Hu et al., Appl. Phys. Lett. 79, 2832 (2001)] we have now deposited high quality SiO2/Si3N4 films over AlGaN with low interface state densities. They have then been used to demonstrate III,N insulating gate transistors (MOSHFET (SiO2) and MISHFET (Si3N4) with gate leakage currents 4,6 order less than those for conventional GaN,AlGaN HFETs. The introduction of the thin insulator layers (less then 100 Å) under the gate increases the threshold voltage by 2,3 V. In addition, it reduces the peak transconductance gm. However the unity cut-off frequency, the gain and the rf-powers remain unaffected as the gm/Cgs (gate-source capacitance) ratio remains unchanged. In addition to managing the defects and gate leakage currents we have also employed InGaN channel double heterojunction structures (AlInGaN,InGaN,GaN) to confine the carriers thereby reducing the spillover into trappings states. These InGaN based MOS-DHFETs exhibited no current-collapse, extremely low gate leakage currents (<10,10 A/mm) and 10,26 GHz rf-powers in excess of 6 W/mm. We have also demonstrated the scalability and stable operation of our new and innovative InGaN based insulating gate heterojunction field effect transistor approach. In this paper we will review the III,N heterojunction field-effect transistors progress and pioneering innovations including the excellent work from several research groups around the world. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Processing approaches of AlGaN/GaN Metal Insulator Semiconductor Hetero Field Effect Transistors (MISHFET) on Si (111) substratesPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue S2 2009Martin Eickelkamp Abstract We report on the fabrication of AlGaN/GaN MISHFETs using SiO2 and SiN as gate dielectrics. In particular, two different passivation procedures are investigated with respect to the resulting electrical properties. A fluorine based ICP etch step, as used here to remove the gate dielectric prior to passivation layer deposition, is shown to deteriorate the sheet carrier concentration and mobility. Depositing the passivation layer upon the gate dielectric, on the other hand, slightly decreases the sheet resistance as compared to a conventional HFET. Gate diode characteristics reveal significant reduction of gate leakage currents in both, reverse and forward biasing regions, of 1-2 and up to 6 orders of magnitude, respectively. All devices exhibit more pronounced current collapse compared to a conventional passivated HFET. In addition, a clear depencency on the processing scheme is observed. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] | |||||||||||||