Home  About us  Contact
 

Gate Array (gate + array)

Distribution by Scientific Domains
Engineering71%

Kinds of Gate Array

  • field programmable gate array
    		•
  • programmable gate array
    		•

    Selected Abstracts

    Visual Tracking and LIDAR Relative Positioning for Automated Launch and Recovery of an Unmanned Rotorcraft from Ships at Sea

    NAVAL ENGINEERS JOURNAL, Issue 2 2009
    MATT GARRATT
    Sensors and systems for a fully autonomous unmanned helicopter have been developed with the aim of completely automating the landing and launch of a small-unmanned helicopter from the deck of a ship. For our scheme, we have combined a laser rangefinder (LRF) system with a visual tracking sensor to construct a low-cost guidance system. Our novel LRF system determines both the distance to and the orientation of the deck in one cycle. We have constructed an optical sensor to complement the laser system, comprising a digital camera interfaced to a Field Programmable Gate Array (FPGA), which enables the entire target tracking computation to be achieved in a very small self-contained form factor. A narrowband light source on the deck is detected by the digital camera and tracked by an algorithm implemented on the FPGA to provide a relative bearing to the deck from the helicopter. By combining the optical sensor bearing with the information from the laser system, an accurate estimate of the helicopter position relative to the deck can be found. [source]

    Embryonic systems implementation with FPGA-based artificial cell network hardware architectures

    ASIAN JOURNAL OF CONTROL, Issue 2 2010
    Csaba Szász
    Abstract The cell-based structure, which makes up the majority of biological organisms, offers the ability to grow with fault-tolerance abilities and self-repair. By adapting these mechanisms and capabilities to nature, scientific approaches have promoted research for understanding related phenomena and associated principles to engine complex novel digital systems and improve their capability. Founded by these observations, the paper is focused on computer-aided modeling, simulation and experimental research of embryonic systems, with the purpose to implement very large scale integrated hardware structures which are able to imitate cells or artificial organism operation mode, with similar robustness and fault-tolerance properties like their biological equivalents from nature. Field Programmable Gate Array (FPGA)-based artificial cell model configuration provided with strongly network communication capabilities is proposed and developed. The presented theoretical and simulation approaches were tested on a laboratory prototype embryonic system (embryonic machine), for study and implementation of basic abilities of living organisms. Copyright © 2010 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society [source]

    Identification and authentication of integrated circuits

    CONCURRENCY AND COMPUTATION: PRACTICE & EXPERIENCE, Issue 11 2004
    Blaise Gassend
    Abstract This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challenge,response protocol. This technique could be used to produce key-cards that are more difficult to clone than ones involving digital keys on the IC. We consider potential venues of attack against our system, and present candidate implementations. Experiments on Field Programmable Gate Arrays show that the technique is viable, but that our current implementations could require some strengthening before it can be considered as secure. Copyright © 2004 John Wiley & Sons, Ltd. [source]

    Modular hardware design for distant-internet embedded systems engineering laboratory

    COMPUTER APPLICATIONS IN ENGINEERING EDUCATION, Issue 4 2009
    Xicai Yue
    Abstract A novel hardware system providing remote accessible embedded system experiments of microcontroller, digital signal processor (DSP), and field-programmable gate array (FPGA) via Internet is presented. Three newly developed hardware modules for integrating experimental boards, experimental instrumentation, and a PC workstation in the distant embedded laboratory are fully described. © 2009 Wiley Periodicals, Inc. Comput Appl Eng Educ 17: 389,397, 2009; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20259 [source]

    A Versatile System for Arbitrary Function Large-Amplitude Fourier Transformed Voltammetry

    ELECTROANALYSIS, Issue 13 2007
    Lishi Wang
    Abstract A novel low-cost instrument for arbitrary function large-amplitude Fourier transformed voltammetry was developed. Description of both hardware and software was given in detail in this paper. A micro-control-unit (MCU) in combination with a field programmable gate array (FPGA) was designed to act as the controller of the instrument. Profiting from the built-in USB2.0 standard interface of the MCU, vast amount of data to/from the high resolution digital-to-analog converter (DAC)/analog-to-digital converter (ADC) then could be exchanged with computer in real-time, instead of being temporarily stored at the capacity limited memory of the instrument which always restricted the length of sampling time and the size of the collected data set. In the [Fe(CN)6]4+/3+ system, by superimposing a sinusoidal waveform with an amplitude of 120,mV onto a triangular potential and then applying to a macro electrode through the instrument, voltammograms up to the eighth harmonic could be well resolved by FT-IFT method. Excellent agreement was attained with Bond's similar experiment [Anal. Chem. 76 (2004) 3619] in respect of the shape and relative peak height of each harmonic. With the simply structured instrument, stable performance, flexible and versatile function was achieved. Arbitrary forms of AC perturbation which may not necessarily be sinusoidal or square-wave or other regular formed periodic signal could be synthesized and superimposed onto a DC potential as the excitation signal with this instrument. Some more useful electrode process information was expected to unveil by utilizing the FT-IFT algorithm to dissect the response signal. [source]

    Real-time signal processing for high-density microelectrode array systems

    INTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, Issue 11 2009
    K. Imfeld
    Abstract The microelectrode array (MEA) technology is continuously progressing towards higher integration of an increasing number of electrodes. The ensuing data streams that can be of several hundreds or thousands of Megabits/s require the implementation of new signal processing and data handling methodologies to substitute the currently used off-line analysis methods. Here, we present one approach based on the hardware implementation of a wavelet-based solution for real-time processing of extracellular neuronal signals acquired on high-density MEAs. We demonstrate that simple mathematical operations on the discrete wavelet transform (DWT) coefficients can be used for efficient neuronal spike detection and sorting. As the DWT is particularly well suited for implementation on dedicated hardware, we elaborated a wavelet processor on a field programmable gate array (FPGA) in order to compute the wavelet coefficients on 256 channels in real-time. By providing sufficient hardware resources, this solution can be easily scaled up for processing more electrode channels. Copyright © 2008 John Wiley & Sons, Ltd. [source]

    Design, implementation and verification through a real-time test-bed of a multi-rate CDMA adaptive interference mitigation receiver for satellite communication

    INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS AND NETWORKING, Issue 1 2003
    Luca Fanucci
    Abstract This paper presents the design, the implementation, and the main performance results of a multi-rate code division multiple access (CDMA) interference mitigation receiver for satellite communication. Such activity was performed within a research project supported by the European Space Agency (ESA), whose aim was to demonstrate the suitability of the linear adaptive interference mitigation detector (IMD) named extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for single-user detection of a CDMA signal in third-generation (3G) satellite networks. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in a blind mode, i.e. it only requires knowledge of the timing of the wanted user's signature code, and is therefore very well suited for integration into handheld user terminals. Experimental results in terms of bit error rate with respect to the theoretical behaviour were derived through a specifically developed test bed. Signal plus multiple access interference generation is performed via a computer-controlled arbitrary waveform generator, followed by frequency up-conversion to the standard intermediate frequency of 70 MHz. Additive white Gaussian noise is then injected with the aid of a precision noise generator. The core of the test bed is a flexible digital receiver prototype featuring the EC-BAID detector plus all functions ancillary to IMD (multi-rate front-end, automatic gain control, code acquisition and tracking, carrier synchronization, etc.). Those functions were implemented through careful mixing of different technologies: field programmable gate arrays (FPGAs) for computing-intensive signal processing functions, digital signal processor (DSP) for housekeeping and monitoring, and application specific integrated circuit (ASIC) for adaptive IMD. The adopted design flow also allows an easy re-use of the prototype architecture to come to an overall integration of the receiver into a single ASIC with modest complexity and power consumption increase with respect to a conventional detector. Copyright © 2003 John Wiley & Sons, Ltd. [source]