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Current Gain (current + gain)
Selected AbstractsDC and small-signal comparison of horizontal emitter designs of InGaP/GaAs heterojunction bipolar transistorsINTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS, Issue 6 2009Juan M. López-González Abstract This paper describes the DC and small-signal performance of two InGaP/GaAs heterojunction bipolar transistors (HBTs) that have the same chip size. This is done in order to compare emitter,base designs using the TCAD ATLAS device simulator. The HBT devices analyzed have the same cutoff and maximum frequencies but significant differences are observed in other characteristics such as base,emitter turn-on voltage, saturation collector,emitter voltage, forward current gain, maximum transducer gain and maximum stable gain. Copyright © 2009 John Wiley & Sons, Ltd. [source] Electric stress effect on DC-RF performance degradation of 0.18-,m MOSFETSMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2006C. C. Chen Abstract We have studied the electric stress effect on DC-RF performance degradation of 64 gate fingers 0.18-,m RF MOSFETs. The fresh devices show good transistor's DC to RF characteristics of small sub-threshold swing of 85 mV/dec, large drive current (Id,sat) of 500 ,A/,m, high unity-gain cut-off frequency (ft) of 47 GHz, and low minimum noise figure (NFmin) of 1.3 dB at 10 GHz. The hot carrier stress for 20% Id,sat reduction causes DC gm and ro degradation as well as the lower RF current gain by 2.35 dB, ft reduction to 35.7 GHz, increasing NFmin to 1.7 dB at 10 GHz and poor output impedance matching. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1916,1919, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21813 [source] The role of doping type in setback layers on wafer-fused AlGaAs/GaAs/GaN HBTsPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 9 2008Chuanxin Lian Abstract The role of doping type in the setback layer of wafer fused AlGaAs/GaAs/GaN HBTs has been investigated. The calculation assuming an ideal GaAs/GaN interface indicates that the current blocking effect due to the conduction band discontinuity between GaAs and GaN can be effectively alleviated by inserting a lightly doped GaAs setback layer with either n-type or p-type doping. And the n-type setback is expected to work better than the p-type setback for the same doping concentration. In experiments encouraging current gain of , 8 was observed in wafer fused HBTs containing 30 nm GaAs setback layers of either n-type or p-type doping, substantially improved from the HBTs without any setback, but still much smaller than annealed as-grown AlGaAs/GaAs/GaAs HBTs. It was proposed that the non-ideal fused interface with a thin disordered material and interface charges/traps dominates the device performance, and that likely both types of fused HBTs (setback doping concentration is , 1 × 1017 cm,3) have similar band diagrams after taking into account impurity redistribution near the interface. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] The role of setback layers on the breakdown characteristics of AlGaAs/GaAs/GaN HBTsPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 6 2008Chuanxin Lian Abstract Breakdown voltages (VCBO) of AlGaAs/GaAs/GaAs and AlGaAs/GaAs/GaAs-setback/GaN HBTs have been compared both theoretically and experimentally with respect to setback layer thicknesses and the doping type. VCBO was calculated using a non-local energy model. The hard breakdown voltage was measured on as-grown GaAs homojunctions and AlGaAs/GaAs/GaN HBTs formed by direct wafer fusion. The calculation showed an increase of VCBO from , 20 V to , 325 V by replacing the GaAs collector with GaN, and VCBO ,90 V was indeed measured. The smaller than predicted VCBO is attributed to the large leakage current currently present in the fused junctions. Insertion of a lightly doped GaAs setback layer has resulted in improved current gain of the fused HBTs, but it also degrades the breakdown characteristics. 20-30 nm setback layers were found to maintain VCBO significantly higher than that of GaAs homojunctions and likely reasonable current gains. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Simulation and implementation of a porous silicon reflector for epitaxial silicon solar cellsPROGRESS IN PHOTOVOLTAICS: RESEARCH & APPLICATIONS, Issue 5 2008Filip Duerinckx Abstract One of the main challenges in the ongoing development of thin film crystalline silicon solar cells on a supporting silicon substrate is the implementation of a long-wavelength reflector at the interface between the epitaxial layer and the substrate. IMEC has developed such a reflector based on electrochemical anodization of silicon to create a multi-layer porous silicon stack with alternating high and low porosity layers. This innovation results in a 1,2% absolute increase in efficiency for screenprinted epitaxial cells with a record of 13·8%. To reach a better understanding of the reflector and to aid in its continued optimization, several extensive optical simulations have been performed using an in-house-developed optical software programme. This software is written as a Microsoft Excel workbook to make use of its user-friendliness and modular structure. It can handle up to 15 individual dielectric layers and is used to determine the influence of the number and the sequence of the layers on the internal reflection. A sensitivity analysis is also presented. A study of the angle at which the light strikes the reflector shows separate regions in the physical working of the reflector which include a region where the Bragg effect is dominant as well as a region where total internal reflection plays the largest role. The existence of these regions is proved using reflection measurements. Based on these findings, an estimate is made for the achievable current gain with an ideal reflector and the potential of epitaxial silicon solar cells is determined. Copyright © 2008 John Wiley & Sons, Ltd. [source] | ||||||||||