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Clock Synchronization (clock + synchronization)

Distribution by Scientific Domains

Information Science and Computing	25%

Selected Abstracts

Clock synchronization in Cell/B.E. traces

CONCURRENCY AND COMPUTATION: PRACTICE & EXPERIENCE, Issue 14 2009
M. Biberstein
Abstract Cell/B.E. is a heterogeneous multicore processor that was designed for the efficient execution of parallel and vectorizable applications with high computation and memory requirements. The transition to multicores introduces the challenge of providing tools that help programmers tune the code running on these architectures. Tracing tools, in particular, often help locate performance problems related to thread and process communication. A major impediment to implementing tracing on Cell is the absence of a common clock that can be accessed at low cost from all cores. The OS clock is costly to access from the auxiliary cores and the hardware timers cannot be simultaneously set on all the cores. In this paper, we describe an offline trace analysis algorithm that assigns wall-clock time to trace records based on their thread-local time stamps and event order. Our experiments on several Cell SDK workloads show that the indeterminism in assigning wall-clock time to events is low, on average 20,40 clock ticks (translating into 1.4,2.8,µs on the system used in our experiments). We also show how various practical problems, such as the imprecision of time measurement, can be overcome. Copyright © 2009 John Wiley & Sons, Ltd. [source]

Clock synchronization for packet networks using a weighted least-squares error filtering technique and enabling circuit emulation service

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 6 2007
James Aweya
Abstract Circuit emulation service (CES) allows time-division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase-locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd. [source]

Clock synchronization using a linear process model

INTERNATIONAL JOURNAL OF NETWORK MANAGEMENT, Issue 1 2006
James Aweya
In this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least-squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals. Copyright © 2006 John Wiley & Sons, Ltd. [source]

Analysis of a clock-recovery technique for circuit emulation services over packet networks

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 1 2008
James Aweya
Abstract One important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high-quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well-known and widely implemented technique for clock recovery in CES is one that is based on packet inter-arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock. Copyright © 2007 John Wiley & Sons, Ltd. [source]

An efficient MAC protocol for multi-channel mobile ad hoc networks based on location information

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 8 2006
Yu-Chee Tseng
Abstract This paper considers the channel assignment problem in a multi-channel MANET environment. We propose a scheme called GRID, by which a mobile host can easily determine which channel to use based on its current location. In fact, following the GSM style, our GRID spends no communication cost to allocate channels to mobile hosts since channel assignment is purely determined by hosts' physical locations. We show that this can improve the channel reuse ratio. We then propose a multi-channel MAC protocol, which integrates GRID. Our protocol is characterized by the following features: (i) it follows an ,on-demand' style to access the medium and thus a mobile host will occupy a channel only when necessary, (ii) the number of channels required is independent of the network topology, and (iii) no form of clock synchronization is required. On the other hand, most existing protocols assign channels to a host statically even if it has no intention to transmit [IEEE/ACM Trans. Networks 1995; 3(4):441,449; 1993; 1(6): 668,677; IEEE J. Selected Areas Commun. 1999; 17(8):1345,1352], require a number of channels which is a function of the maximum connectivity [IEEE/ACM Trans. Networks 1995; 3(4):441,449; 1993; 1(6): 668,677; Proceedings of IEEE MILCOM'97, November 1997; IEEE J. Selected Areas Commun. 1999; 17(8):1345,1352], or necessitate a clock synchronization among all hosts in the MANET [IEEE J. Selected Areas Commun. 1999; 17(8):1345,1352; Proceedings of IEEE INFOCOM'99, October 1999]. Through simulations, we demonstrate the advantages of our protocol. Copyright © 2005 John Wiley & Sons, Ltd. [source]

Improved artifact correction for combined electroencephalography/functional MRI by means of synchronization and use of vectorcardiogram recordings

JOURNAL OF MAGNETIC RESONANCE IMAGING, Issue 3 2008
Karen J. Mullinger BSc
Abstract Purpose To demonstrate that two methodological developments (synchronization of the MR scanner and electroencephalography [EEG] clocks and use of the scanner's vectorcardiogram [VCG]) improve the quality of EEG data recorded in combined EEG/functional MRI experiments in vivo. Materials and Methods EEG data were recorded using a 32-channel system, during simultaneous multislice EPI acquisition carried out on a 3 Tesla scanner. Recordings were made on three subjects in the resting state and on five subjects using a block paradigm involving visual stimulation with a 10-Hz flashing checkerboard. Results Gradient artifacts were significantly reduced in the EEG data recorded in vivo when synchronization and a TR equal to a multiple of the EEG clock period were used. This was evident from the greater attenuation of the signal at multiples of the slice acquisition frequency. Pulse artifact correction based on R-peak markers derived from the VCG was shown to offer a robust alternative to the conventionally used ECG-based method. Driven EEG responses at frequencies of up to 60 Hz due to the visual stimulus could be more readily detected in data recorded with EEG and MR scanner clock synchronization. Conclusion Synchronization of the scanner and EEG clocks, along with VCG-based R-peak detection is advantageous in removing gradient and pulse artifacts in combined EEG/fMRI recordings. This approach is shown to allow the robust detection of high frequency driven activity in the EEG data. J. Magn. Reson. Imaging 2008;27:607,616. © 2008 Wiley-Liss, Inc. [source]

Maximum likelihood estimators of clock offset and skew under exponential delays

APPLIED STOCHASTIC MODELS IN BUSINESS AND INDUSTRY, Issue 4 2009
Jun Li
Abstract Accurate clock synchronization is essential for many data network applications. Various algorithms for synchronizing clocks rely on estimators of the offset and skew parameters that describe the relation between times measured by two different clocks. Maximum likelihood estimation (MLE) of these parameters has previously been considered under the assumption of exponentially distributed network delays with known means. We derive the MLEs under the more common case of exponentially distributed network delays with unknown means and compare their mean-squared error properties to a recently proposed alternative estimator. We investigate the robustness of the derived MLE to the assumption of non-exponential network delays, and demonstrate the effectiveness of a bootstrap bias-correction technique. Copyright © 2009 John Wiley & Sons, Ltd. [source]