CMOS Technology (cmo + technology)

Distribution by Scientific Domains
Engineering95%
2 Other Domains5%

Kinds of CMOS Technology

  • nm cmo technology
    		•

    Selected Abstracts

    A dc I,V model for short-channel polygonal enclosed-layout transistors

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 2 2009
    Paula López
    Abstract Despite the demonstrated radiation immunity of gate-enclosed layout transistors in deep submicron CMOS technologies, there is a significant lack of a thorough theoretical study addressing fundamental design issues on this kind of transistors. In this paper we propose a physical dc I,V model for short-channel polygonal-shape enclosed-layout transistors in both the linear and saturation regions of operation accounting for second-order effects such as depletion region non-uniformity, carrier velocity and channel length modulation. The impact of this layout style on the driving capability of the devices is also investigated. Experimental results based upon a fabricated NMOS test chip containing these devices in a standard 0.18µm CMOS technology process are presented. The comparison of the theoretical prediction with the experimental data show close agreement. Copyright © 2008 John Wiley & Sons, Ltd. [source]

    Low power switched-current circuits with low sensitivity to the rise/fall time of the clock

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 5 2010
    Radek Rudnicki
    Abstract The switched-current (SI) technique permits realizing analog discrete-time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented. It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35µm CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35µm CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first-order filter is built with the use of elementary cells on the chip. Copyright © 2008 John Wiley & Sons, Ltd. [source]

    LC-active VCO for CMOS RF transceivers

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 1 2010
    Domenico Zito
    Abstract A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ,boot-strapped inductor' (BSI), which behaves like a high-quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5,6,GHz direct-conversion multi-standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high-quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9,mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93,GHz (nearly equal to 19%). The circuit exhibits a PN of ,129dBc/Hz at 1,MHz of frequency offset from the central frequency (5.4,GHz) and a FOM equal to 189.5,dBc/Hz at 100,kHz and 194.1,dBc/Hz at 1,MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd. [source]

    Current-mode filters based on current mirror arrays

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 2 2008
    George Souliotis
    Abstract A technique is proposed for obtaining current-mode filters based on current mirror arrays that operate as unity gain current amplifiers. These amplifiers by properly driving capacitors realize active lossless integrators which are the basic active elements for the derivation of filters according to the leapfrog method. Due to the fact that both the structure of the amplifiers and the adapted method for filter design are simple, the proposed technique is attractive for filter design and implementation. A design and the implementation of two third-order low-pass filters are presented. The array of the amplifiers has been implemented in a 0.8 µm CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd. [source]

    ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 2-3 2002
    G. Liñán
    Abstract This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 µm standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time (<300 ns for linear convolutions) and using a low power budget (<1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with >7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 template,-either directly or through template decomposition. This means the 100% of the 3×3 linear templates reported in Roska et al. 1998, [1]. Copyright © 2002 John Wiley & Sons, Ltd. [source]

    Compact CMOS implementation of a low-power, current-mode programmable cellular neural network,

    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 3 2001
    L. Ravezzi
    Abstract We report on the design and characterization of a full-analog programmable current-mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell-core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low-power consumption and small-area occupation, making it suitable for the realization of large cell-grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey-scale and binary image processing tasks. Results from the characterization of a preliminary CNN test-chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd. [source]

    Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high-speed switch/router,

    INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 2 2009
    Ling Wu
    Abstract Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high-speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst-case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer-sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer-sharing scheme by both a numerical model and extensive simulations under uniform and non-uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high-speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd. [source]

    A scalable advanced RF IC design-oriented MOSFET model,

    INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 4 2008
    Matthias Bucher
    Abstract This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The scaling behaviour over a large range of channel lengths and bias conditions is presented. Long-channel devices show significant non-quasi static effects while in short-channel devices the parasitics modelling is critical. This is illustrated with Y-parameters and ft vs. ID in NMOS and PMOS devices, showing good overall RF modelling abilities of the EKV3 MOSFET model. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008. [source]

    Analysis and design of a fully integrated CMOS low-noise amplifier for concurrent dual-band receivers

    INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 5 2006
    Y. P. Zhang
    Abstract This article thoroughly analyzes a concurrent dual-band low-noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual-band LNA. As an example of the analysis, a fully integrated dual-band LNA is designed in a standard 0.18-,m 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high-band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5-V supply voltage and achieves voltage gains of 14 and 22 dB, input S11 of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006. [source]

    A low-phase-noise CMOS quadrature VCO with PMOS back-gate coupling

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 12 2010
    Mei-Ling Yeh
    Abstract A new PMOS backgate quadrature voltage controlled oscillator (QVCO) is designed and implemented using TSMC 0.18 ,m 1P6M CMOS technology. The phase noise of the PMOS back-gate coupled QVCO operating at 1.5 V is measured to be ,100 dBc/Hz and ,125.08 dBc/Hz at 100 KHz and 1 MHz offset, respectively, for a low power consumption of 15 mW. The backgate QVCO demonstrates a wide frequency tuning range, a low phase noise, and a low power consumption. The corresponding figure-of-merit of the QVCO is ,186 dBc/Hz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2682,2685, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25564 [source]

    A 60-GHz CMOS receiver front-end with integrated 180° out-of-phase Wilkinson power divider

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 12 2010
    Jen-How Lee
    Abstract A 60-GHz receiver front-end with an integrated 180° out-of-phase Wilkinson power divider using standard 0.13 ,m CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA) with 12.4-dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180° out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input return loss at RF port better than ,10 dB for frequencies from 52.3 to 62.3 GHz. At IF of 20 MHz, the receiver front-end achieved maximum conversion gain of 18.7 dB at RF of 56 GHz. The corresponding 3-dB bandwidth (,3 dB) of RF is 9.8 GHz (50.8,60.6 GHz). The measured minimum noise figure (NF) was 9 dB at 58 GHz, an excellent result for a 60-GHz-band CMOS receiver front-end. In addition, the measured input 1-dB compression point (P1 dB) and input third-order inter-modulation point (IIP3) are ,20.8 dBm and ,12 dBm, respectively, at 60 GHz. These results demonstrate the adopted receiver front-end architecture is very promising for high-performance 60-GHz-band RFIC applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2688,2694, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25559 [source]

    An efficient CMOS power-combining technique with differential and single-ended power amplifier

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2010
    Eunil Cho
    Abstract This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-,m CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2214,2217, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25460 [source]

    A low voltage balanced Clapp VCO in 0.13 micromolar CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 7 2010
    Sheng-Lyang Jang
    Abstract A balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 ,m CMOS 1P8M process. The designed VCO circuit topology is an all nMOS LC-tank Clapp VCO using a series-tuned resonator. At the supply voltage of 0.5 V, the output phase noise of the VCO is ,108.69 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 17.72 GHz, and the figure of merit is ,186.84 dBc/Hz. The core power consumption is 4.2 mW. Tuning range is about 3.32 GHz, from 17.55 to 20.87 GHz, while the control voltage was tuned from 0 to 1.3 V. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1623,1625, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25275 [source]

    A variable gain amplifier using a very-high speed OTA

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 5 2010
    You Zheng
    Abstract A variable gain amplifier is demonstrated using only one fully-differential operational transconductance amplifier (OTA) as the core circuit element.Gain control is achieved by varying the transconductance of the OTA and by using an output buffer circuit to sum the output signals of the OTA in the correct phase relationship. The circuit was designed and fabricated using 0.18 ,m CMOS technology. Measured results show a gain control range of 15 dB between 1 GHz and 3 GHz and the input and output reflection coefficients are below ,10 dB and ,20 dB, respectively. The output power of the amplifier is +2.3 dBm at its 1-dB compression point. The chip has a maximum DC power consumption 12.6 mW and it measures 0.25 mm2 including bonding pads. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1112,1116, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25114 [source]

    Low-voltage/low-power 7-GHZ transformer-coupled current-reused CMOS QVCO with wide tuning range

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2010
    Yan-Ru Tseng
    Abstract In this article, we report the design of a transformer-coupled current-reused quadrature voltage-controlled oscillator (QVCO) having low-voltage operation, low-power consumption, and a wide tuning range. An improved trifilar transformer that is fabricated by symmetrically interlacing two half circle secondary coils between the turns of the primary coil is proposed to provide a higher magnetic coupling factor. A QVCO integrated with such a trifilar transformer is implemented using 0.18-,m RF CMOS technology. When the QVCO is operated at a supply voltage of 1V at 7.263 GHz, the measured phase noise is ,111.4 dBc/Hz at a 1-MHz offset. Further, the QVCO core draws only 1.58 mW. The total tuning range is ,510 MHz over the whole tuning range (from 0 to 1.8 V). The calculated figure of merit is 186.6 dB and the power-frequency-tuning-normalized factor is ,9.4 dB. As compared to the reported data in a previous study, a 28.2% reduction in power consumption and a 54.5% increase in tuning range can be achieved. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:797,801, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25058 [source]

    Complementary predistorter in CMOS differential power amplifier

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2010
    Inn-Yeah Oh
    Abstract For adaptive improvement of linearity above a 12 dB PAPR for 64QAM WiMAX, a complementary feedback loop in a differential amplifier is adopted as a pre-distorter that is realized using an NMOS cell operating in the triode region in order to compensate the gm3, the third order transconductance, of the differential amplifier. The power amplifier has been implemented in 0.18 ,m CMOS technology, and the chip size is 870 ,m × 1050 ,m. The proposed PA obtains the 42% efficiency at P1dB while improving the IMD by more than 10 dB above 15 dBm output power levels. It shows a gain of as much as 14.5 dB, and a return loss below ,12 dB for 2.3,2.4 GHz operation. Finally, the fabricated PA complies with the spurious emission of WiMAX standards up to 22 dBm. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:833,836, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25062 [source]

    A novel tunable dual-band low noise amplifier for 868/915 MHz and 2.4 GHz Zigbee application by CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2010
    Kai Xuan
    Abstract A dual-band (868/915 MHz and 2.4 GHz) low noise amplifier for Zigbee applications is designed using 0.35-,m CMOS technology. At 868/915 MHz and 2.4 GHz, the gains achieved are both 16 dB and the resulting noise figures are about 2.5 dB and 2.7 dB, respectively. The input and the output reflections are below ,10 dB in both bands. The amplifier works at 2.5 V supply voltage with 12 mA current dissipation. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 507,510, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24964 [source]

    A 2.4 GHz CMOS diversity receiver having a soft-start regulator for wake-up

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2010
    Yong-iL Kwon
    Abstract An improved diversity receiver having a new regulator for stable power supply in a 0.18 ,m CMOS technology is presented. The regulator with soft-start is implemented to eliminate the battery damages at initial power-up. To reduce the external components, two switches for antenna diversity are integrated in front of LNA on the chip. A stacked inductor technique is adopted to reduce the chip area. The simulation and measurement results show that the soft-start time of the regulator can be controlled by a variable resistor from 200 ,S to 6.2 mS. The front-end (LNA and mixer) can achieve a voltage gain of 33.5 dB, a noise figure (NF) of 3.8 dB, and 23 dB of the isolation between antennas when consuming 3.9 mW with a 1.8 V power supply. The NF includes the loss of a BALUN, BPF, and switches. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 611,615, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25000 [source]

    Design and implementation of a high-performance V-band CMOS bandpass filter

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 2 2010
    Jin-Fa Chang
    Abstract In this article, we demonstrate a low-insertion-loss V-band (50,75 GHz) bandpass filter with two finite transmission zeros by standard 0.13 ,m CMOS technology. The proposed filter architecture has the following feature: the low-frequency transmission-zero and the high-frequency transmission-zero can be tuned by the series-feedback capacitor Cs and the parallel-feedback capacitor Cp, respectively. Besides, low-insertion-loss is achieved by adopting thick microstrip-line (MSL) with optimized ground-plane pattern as the needed inductors to minimize the metal and substrate loss. This filter achieved insertion-loss (1/S21) lower than 3 dB over the frequency range of 52.2,76.7 GHz, input return loss (S11) better than ,10 dB over the frequency range of 50.2,80.6 GHz, and output return loss (S22) better than ,10 dB over the frequency range of 50.2,77.3 GHz. The minimum insertion-loss was 2.18 dB at 63.5 GHz, an excellent result for a V-band CMOS bandpass filter. The chip area was only 0.466 × 0.307 mm2, i.e., 0.143 mm2, excluding the test pads. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 309,316, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24935 [source]

    Low power wide-locking range CMOS quadrature injection-locked frequency divider

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2009
    Sheng-Lyang Jang
    Abstract This letter presents a new low power and wide-locking range divide-by-2 injection-locked frequency divider (ILFD). The ILFD consists of a new 5.35 GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18 ,m CMOS technology and the core power consumption is 5.72 mW at the supply voltage of 0.8 V. The free-running frequency of the QILFD is tunable from 5.24 to 5.55 GHz. At the input power of 0 dBm, the divide-by-2 locking range is from 8.2 to 13.3 GHz as the tuning voltage is biased at 0.8 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the divide-by-2 mode. The phase deviation of quadrature output is about 1.28°. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2420,2423, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24640 [source]

    A 42-GHz transmitter linearization using predistortion IF amplifier

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 6 2009
    Jeng-Han Tsai
    Abstract This article presents a millimeter-wave (MMW) transmitter linearization using predistortion IF amplifier. The predistortion IF amplifier was designed in 0.18-,m CMOS technology at 2.4 GHz. It can provide predistortion function at IF port to linearize the whole MMW transmitter. The 42-GHz transmitter module is custom design. After linearization, 8 dB ACPR improvement of the 42-GHz MMW transmitter module can be achieved. The linear output power of the 42-GHz transmitter module has been increased 2 dBm for the same linearity requirements. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1450,1452, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24351 [source]

    A 60-GHz low-noise amplifier for 60-GHz dual-conversion receiver

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2009
    Yo-Sheng Lin
    Abstract A 60-GHz-band low-noise amplifier (LNA) using bulk 65-nm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascade common-source stages followed by a cascode output stage. Current-sharing technique is adopted in the second and third stage to reduce power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain over the 57,64-GHz-band of interest. This LNA achieved input return loss (S11) of ,10.6 to ,37.4 dB, voltage gain (AV) of 10.7,18.8 dB, reverse isolation (S12) of ,43.5 to ,48.1 dB, input referred 1-dB compression point (P1dB-in) of ,16.2 to ,20.8 dBm, and input third-order intermodulation point (IIP3) of ,4 to ,7.5 dBm over the 57,64-GHz-band of interest. It consumed only a small DC power of 21.4 mW. In addition, the chip area was only 0.849 × 0.56 mm2, including all the test pads and bypass capacitors. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 885,891, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24200 [source]

    A 5.79-dB NF, 30-GHz-band monolithic LNA with 10 mW power consumption in standard 0.18-,m CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 4 2009
    Chi-Chen Chen
    Abstract A 30-GHz (Ka-band) low-noise amplifier (LNA) with 10 mW power consumption (PDC) using standard 0.18-,m CMOS technology was designed and implemented. To achieve sufficient gain, this LNA was composed of three cascade common-source stages, and a series peaking inductor (Lg3) was added to the input terminal of the third stage to boost the peak gain (S21-max) from 11.7 (at 28.8 GHz) to 14.5 (at 28 GHz), i.e., 23.9% (simulation). Shunt RC feedback was adopted in the third stage for achieving good output impedance matching. At 30 GHz, this LNA achieved excellent input return loss (S11) of ,19.5 dB, output return loss (S22) of ,23.8 dB, forward gain (S21) of 11.1 dB, reverse isolation (S12) of ,49.2 dB, and noise figure of 5.79 dB. The corresponding gain/PDC was 1.11, which is better than those of the CMOS LNAs around 30 GHz reported in the literature. The measured input-referred 1-dB compression point (P1dB-in) and input third-order intermodulation point (IIP3) were ,10.9 and ,2 dBm, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 933,937, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24250 [source]

    A 2.4/5.7-GHz dual-band low-power CMOS RF receiver with embedded band-select switches

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2009
    D.-R. Huang
    Abstract This article presents a 2.4-/5.7-GHz dual-band low-power direct-conversion CMOS RF receiver for the 802.11a/b/g WLAN applications. The RF receiver includes a low noise amplifier (LNA) with dual input stages and dual switches for each of 2.4/5.7-GHz applications. This design can substitute the use of two LNAs in conventional structure and eliminate the use of the costly external band-select switches. It also alleviates the difficulty of single matching for multiple frequency bands. The RF receiver also includes a Gilbert-cell-based broadband mixer which is designed to be both low power consumption and relatively high conversion gain. Fabricated in 0.18-,m CMOS technology, the RF receiver exhibits a conversion gain of 25.8/20.6 dB, DSB noise figure of 4.4/5.6 dB, and input IP3 of ,18/,12.5 dBm at 2.4/5.7 GHz frequency band, respectively. The measured EVM for IEEE 802.11a/b/g is 1.2/1.6/1.1% at data rate of 11/54/54 Mbps. The power consumption under 1.8 V supply is 10.6 mW for the 2.4 GHz mode, and 17.2 mW for the 5.7 mode. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 593,597, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24120 [source]

    60-GHz bandpass filter with ACMRC resonator fabricated using 0.18-,m CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2009
    Chia-Hsieh Liu
    Abstract This article presents design and implementation of a 60-GHz millimeter- wave on-chip bandpass filter using a 0.18-,m standard CMOS process. The asymmetric compact microstrip resonator cell structure is used to design the filter with two transmission zeros. The input and output capacitors using multilayer coupling are added to create the passband. The die size of the chip is 0.85 × 0.64 mm2. The filter has a 3-dB bandwidth of about 15 GHz at the center frequency of 64 GHz. The measured insertion loss of the center-frequency is about 3.9 dB and the return loss is better than 10 dB within passband. The designed on-chip filter is useful for the integrated design of the 60-GHz CMOS single-chip RF transceiver. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 597,600, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24119 [source]

    A low power low noise amplifier with subthreshold operation in 130 nm CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 11 2008
    Ickhyun Song
    Abstract In this article, a 5.8 GHz ISM-band CMOS low noise amplifier (LNA) operating in a subthreshold region is presented. A conventional source degeneration inductor is eliminated for higher signal gain while providing reasonable input impedance. The LNA is fabricated using 130 nm CMOS technology and measured signal gain, noise figure, and power consumption are 13.4 dB, 5.2 dB, and 980 ,W, respectively, at target frequency. Also the LNA achieves the highest figure of merit among the recently published subthreshold LNAs. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2762,2764, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23788 [source]

    Size reduction of microwave and millimeter-wave passive circuits by UC-PBG in standard 0.18-,m CMOS technology

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2008
    Shuiyang Lin
    Abstract Size reduction of microwave and millimeter-wave (mm-wave) passive circuits incorporating a defective uniplanar compact photonic bandgap (UC-PBG) slow-wave structure is investigated. Benefited from the multilayer mental technology of the standard 0.18-,m CMOS process, thin film microstrip structure is properly constructed on the lossy silicon substrate to reduce substrate loss. Defected periodic patterns on the ground plane are used to contribute to an enhancement of the effective dielectric constant and the slow-wave factor is 14% increased by the use of UC-PBG ground. Microwave and mm-wave passive circuits including resonator and filter are designed and fabricated. Measured results show that the use of UC-PBG ground has induced a frequency drop of 14% and validate the size reduction concept by using UC-PBG. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2251,2254, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23643 [source]

    Small size low noise amplifier with suppressed noise from gate resistance

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2008
    Ickhyun Song
    Abstract In this article, design and characterization results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13-,m CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated to achieve smaller chip area while providing reasonable 50-, matching. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the designed LNA occupies total area of 0.68 mm2 and the results show forward power gain (S21) of 12.7 dB and noise figure of 3.9 dB while consuming 6.85 mW from 1.2-V DC supply. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2300,2304, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23702 [source]

    A CMOS opto-electronic single chip using the hybrid scheme for optical receivers

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2008
    Jian-Ming Huang
    Abstract An opto-electronic integrated circuit based on the hybrid scheme for an optical receiver front-end is presented in this article. The proposed integrated circuit adopts the CMOS technology as the vehicle to integrate the InP-based waveguide photodetector into the transimpedance amplifier (TIA) circuit. A regulated cascade structure is used to reduce the input impedance of the TIA. Hence, the proposed integrated circuit can achieve a very high bandwidth provided that the parasitic capacitance of the photodetector is up to 1 pF. The 3-dB bandwidth and the transimpedance gain of the proposed circuit are 1 GHz and 64.5 dB,, respectively. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2430,2434, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23693 [source]

    A low-power V-band CMOS low-noise amplifier using current-sharing technique

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 7 2008
    Hong-Yu Yang
    Abstract A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 ,m CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and four stages to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (AV) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1dB-in) of ,20 dBm, and input third-order inter-modulation point (IIP3) of ,9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91 × 0.58 mm2, including all the test pads and bypass capacitors. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1876,1879, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23523 [source]