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CMOS Process (cmo + process)
Kinds of CMOS Process Selected AbstractsPlasma Polymer Surfaces Compatible with a CMOS Process for Direct Covalent Enzyme ImmobilizationPLASMA PROCESSES AND POLYMERS, Issue 1 2009Yongbai Yin Abstract Plasma polymerized surfaces, prepared using a CMOS compatible plasma enhanced chemical vapor polymerization technique, are found to covalently immobilize enzymes without the need for intermediate chemical linker groups. The polymerized surfaces are smooth, strongly adherent to substrates, and have a long shelf life for storage. After incubation with enzymes, a densely packed monolayer is attached. We report the effects of both oxygen etching and annealing post-processing showing that they can be implemented so as not to affect the enzyme binding performance. The fully compatible polymerization method with CMOS device manufacture processes is a potential candidate for integration into nano-CMOS biochemical sensors for direct immobilization of enzymes. [source] A highly sensitive thermosensing CMOS Circuit Based on self-biasing circuit techniqueIEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 2 2009Tetsuya Hirose Non-memebr Abstract A thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed. The circuit is based on a self-biasing circuit technique and uses the temperature-sensitive characteristics of MOSFETs operating in the subthreshold region. To develop this sensor device, a method to analyze self-biasing circuits, which is different from a conventional one, was employed. This method is useful for understanding the self-biasing circuit operation. A temperature sensor device makes use of a MOSFET resistor's transition from a strong inversion to a weak-inversion or subthreshold operation. The temperature at which the transition occurs can be set to a desired value by adjusting the parameters of MOSFETs in the circuit. The sensor LSI can be made using a standard CMOS process and can be used as over-temperature and over-current protectors for LSI circuits. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source] High efficiency DC,DC converter for wide-ranging loads with gradual reverse current stopping techniqueIEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 6 2008Kouhei Yamada Member Abstract A novel reverse current stopping technique for synchronous rectifiers in DC,DC converters is proposed. It is based on gradual adjustment of the ON-time of the synchronous rectifier to finally stop the reverse current. Therefore, delay to detect and stop reverse current does not cause extra reverse current, so almost perfect reverse current stopping can be achieved with small DC power consumption. An example circuit of the proposed technique was designed and included in a fixed ON-time pulse frequency modulation (PFM) control DC,DC converter. The designed converter was fabricated in the 0.35 µm CMOS process, and then its operation was verified. Copyright © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source] A switched-capacitor programmable gain amplifier using dynamic element matchingIEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 6 2007Jun Wang Non-member Abstract This paper discusses the effect of capacitor mismatch errors on gain accuracy of switched-capacitor programmable gain amplifier (SC PGA). To improve gain deviations caused by mismatch errors, the dynamic element matching (DEM) algorithm is applied to the SC PGA circuits. It uses digital gain-control signal to dynamically vary the matched capacitor combinations so that the effective capacitances of the sampling and feedback capacitor arrays are averaged, and thus the gain deviations due to capacitor mismatch errors are eliminated to a significant extent. The distortion caused by mismatch errors shift to certain frequency bands, and could be reduced or removed by subsequent processing such as lowpass filtering. A 4-bit SC PGA using DEM was designed in 0.25 µm CMOS process with 2.5 V voltage supply, including offset cancellation and clock bootstrapped circuits operating at a sampling frequency of 10 MHz. Test results have indicated that gain deviations due to mismatch errors are substantially reduced. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source] Explicit design formulas for current-mode leap-frog OTA-C filters and 300,MHz CMOS seventh-order linear phase filterINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 4 2010Yichuang Sun Abstract The leap-frog (LF) configuration is an important structure in analogue filter design. Voltage-mode LF OTA-C filters have recently been studied in the literature; however, general explicit formulas do not exist for current-mode LF OTA-C filters and there is also need for current-mode LF-based OTA-C structures for realization of arbitrary transmission zeros. Three current-mode OTA-C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all-pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all-pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300,MHz seventh-order linear phase low-pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5,V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320,MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/,Hz, dynamic range is 66,dB and power consumption is 200,mW. Copyright © 2008 John Wiley & Sons, Ltd. [source] CMOS digitally programmable quadrature oscillatorsINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 8 2008Hussain A. Alzaher Abstract CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier-based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage-mode and current-mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35,µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd. [source] Using MOS current dividers for linearization of programmable gain amplifiersINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 4 2008M. Teresa Sanz Abstract Two highly linear, digitally programmable gain amplifiers are presented and compared in terms of linearity, frequency, area and power consumption. High linearity and wide gain tuning range with moderate area consumption are the main benefits of both configurations. Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three-bit prototypes were integrated in a 0.35,µm,3.3,V CMOS process with 2.5,V supply voltage. Experimental distortion levels are better than ,68,dB for 1,MHz and 1,Vp,p output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown. Copyright © 2007 John Wiley & Sons, Ltd. [source] Modelling of source-coupled logic gatesINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 4 2002M. Alioto Abstract In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single-pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil-and-paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35-µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil-and-paper evaluations and for computer-based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley & Sons, Ltd. [source] An efficient CMOS power-combining technique with differential and single-ended power amplifierMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2010Eunil Cho Abstract This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-,m CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2214,2217, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25460 [source] A novel CMOS distributed receiver front-end for wireless ultrawideband receiversMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2010Xin Guan Abstract An ultrawideband CMOS distributed receiver front-end utilizing cascade gain cell structure is designed in Jazz 0.18-,m CMOS process. The proposed distributed front-end, fully integrating a low-noise amplifier (LNA) and mixer together, demonstrates 11.5,14 dB gain, 5,6.5 dB noise figure and more than 9-dB RF/LO return loss over 2,17 GHz with a fixed IF frequency of 500 MHz and LO power of 5 dBm. The entire circuit occupies 1.7 × 1.0 mm2 including on-wafer pads and consumes 170 mA from 1.8-V voltage supply. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1790,1792, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25316 [source] A CMOS differential fifth-derivative Gaussian pulse generator for UWB applicationsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2010Jin He Abstract A CMOS differential fifth-derivative Gaussian pulse generator is presented for Ultrawideband (UWB) applications. The design exhibits low-power consumption, low-circuit complexity, and precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The proposed differential pulse generator was implemented with a 1.8-V, 0.18-,m CMOS process, but only the positive fifth-derivative Gaussian pulse was measured owing to the limitation of the available testing facilities. The measured pulse has peak-to-peak amplitude of 154 mV and a pulse width of 820 ps. Small core area of the differential pulse generator is only 0.028 mm2 because of its all digital circuit design. The average power dissipation is 1.2 mW with a pulse repetition frequency (PRF) of 50 MHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1849,1852, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25342 [source] A 90 nm CMOS dual-band divide-by-2 and -4 injection-locked frequency dividerMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 6 2010Sheng-Lyang Jang Abstract A fourth-order resonator has been implemented to design a 65 GHz injection-locked frequency divider (ILFD) implemented in a 90 nm CMOS process. The ILFD is realized with a cross-coupled nMOS LC-tank oscillator with an inductor switch for frequency band selection. The LC tank can be a second-or fourth-order resonator depending upon the on/off state of a switch across a series-tuned inductor. Measurement results show that at the supply voltage of 0.5 V, the free-running frequency is from 8.68 (16.147) to 9.928 (17.89) GHz for the low- (high-) frequency band. The divide-by-2 operational locking range is from 14.9 (30.64) to 22.2 (37.74) GHz for the low-(high)-frequency band. The divide-by-4 operational locking range is from 34.4 (64.6) to 40.35 (67) GHz for the low-(high)-frequency band. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1421,1425, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25217 [source] A fully integrated ultra-low power CMOS transmitter module for UWB systemsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2009Tao Yuan Abstract A fully integrated CMOS ultra-wideband (UWB) transmitter module is proposed for UWB applications. The transmitter module consists of a band-notched UWB antenna and a transmitter IC which integrates a pulse generator, a gating signal generator and driver amplifiers (DAs). The drive amplifier uses a two-stage amplifier,a Class-E amplifier and a Class-A amplifier with switch control, to significantly reduce power consumption (522 ,W/20 Mbps). Fabricated using a 0.18-,m CMOS process, the generated pulse then passes through the DA, which not only drives the antenna but also shapes the generated digital signal to meet the Federal Communications Commission spectral mask specification. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2318,2323, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24632 [source] A 5-GHz low-phase noise CMOS VCO with swing boosting techniqueMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2009Junhua Liu Abstract A 5-GHz CMOS VCO with improved phase noise is proposed in this article. A gate voltage boosting technique is realized with only one inductor. The proposed VCO is fabricated in 0.18 ,m CMOS process, and the measured phase noise is ,122.7 dBc/Hz@1 MHz when operates at 4.936 GHz, with a power dissipation of 5.28 mW from 1 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2061,2064, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24539 [source] Low-loss and high-isolation active type cascode switch in 0.13-,m CMOS for millimeter-wave applicationsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2009Dong Ho Lee Abstract This article presents two types of switches which are fabricated in 0.13-,m standard CMOS process characterized up to 50 GHz. The first is the conventional series NMOS switch with an optimum gate width which is adjusted by measuring various sized devices. The second is a new active type cascode switch for millimeter-wave phased array systems. The series NMOS switch produces 3 dB insertion loss and 7.5 dB isolation at 40 GHz. In contrast, the active type cascode switch has 7.5 dB better insertion loss (Gain) and 20 dB better isolation than the passive switch at 40 GHz. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1856,1858, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24476 [source] 60-GHz bandpass filter with ACMRC resonator fabricated using 0.18-,m CMOS technologyMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2009Chia-Hsieh Liu Abstract This article presents design and implementation of a 60-GHz millimeter- wave on-chip bandpass filter using a 0.18-,m standard CMOS process. The asymmetric compact microstrip resonator cell structure is used to design the filter with two transmission zeros. The input and output capacitors using multilayer coupling are added to create the passband. The die size of the chip is 0.85 × 0.64 mm2. The filter has a 3-dB bandwidth of about 15 GHz at the center frequency of 64 GHz. The measured insertion loss of the center-frequency is about 3.9 dB and the return loss is better than 10 dB within passband. The designed on-chip filter is useful for the integrated design of the 60-GHz CMOS single-chip RF transceiver. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 597,600, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24119 [source] An X-band 185° CMOS phase shifter MMIC for multiple-antenna systemsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2009Chien-San Lin Abstract The design and implementation of an X-band phase shifter MMIC using the standard 0.18-,m CMOS process is presented. A transformed doublet varactor load is analyzed and applied to a 3-dB quadrature coupler to exhibit large phase shift tuning range and low insertion loss with minimal variation. By using the derived design equations, the implemented CMOS reflection-type phase shifter demonstrates a continuous phase shift tuning range greater than 185°, an average insertion loss of 5.2 dB with ±0.4 dB variation, and return losses better than 13 dB in 9,11 GHz. The total chip size including I/O pads is 0.76 × 0.79 mm2. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 645,648, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24131 [source] An efficient CMOS on-chip ladder reflector antenna for inter-chip communicationsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 1 2009Bo-Tao Jiang Abstract This article presented a new ladder reflector antenna on chip (AOC) which consisted of an active dipole and reflector array. The ladder structure was very easy to fabricate with the standard CMOS process. A ladder reflector antenna operating at the 24 GHz ISM band was designed with a standard 0.18 ,m six metal layers CMOS process. The whole antenna had a dimension of 0.025 mm × 2.84 mm. The measurement results showed that the ladder reflector antenna got a return loss of ,7.25 dB and a gain of 6.25 dBds at 24 GHz, as well as a ,5 dB impedance bandwidth of 16.2,30 GHz. The measured S12 indirectly proved the simulated radiation patterns. The data taken from the experiment indicated that the ladder reflector increased the antenna gain and effectively enhanced the energy radiating to the outside of the chip. It's very useful for the wireless interconnect for inter-chip communications. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 59,63, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24000 [source] Size reduction of microwave and millimeter-wave passive circuits by UC-PBG in standard 0.18-,m CMOS technologyMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2008Shuiyang Lin Abstract Size reduction of microwave and millimeter-wave (mm-wave) passive circuits incorporating a defective uniplanar compact photonic bandgap (UC-PBG) slow-wave structure is investigated. Benefited from the multilayer mental technology of the standard 0.18-,m CMOS process, thin film microstrip structure is properly constructed on the lossy silicon substrate to reduce substrate loss. Defected periodic patterns on the ground plane are used to contribute to an enhancement of the effective dielectric constant and the slow-wave factor is 14% increased by the use of UC-PBG ground. Microwave and mm-wave passive circuits including resonator and filter are designed and fabricated. Measured results show that the use of UC-PBG ground has induced a frequency drop of 14% and validate the size reduction concept by using UC-PBG. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2251,2254, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23643 [source] Low cost ultra wideband amplifier in 0.35 ,m CMOS processMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 7 2008Kuldip N. Modha Abstract A two stage ultra wideband (UWB) amplifier is presented. This amplifier incorporates multiple bandwidth enhancing techniques and is implemented in Austria micro systems (AMS) 0.35 ,m CMOS process technology. The amplifier consumes 39.5 mW of power, exhibits a maximum gain of 13 dB, has input and output reflections below ,9 and ,10 dB, respectively over a ,3 dB bandwidth of 4 GHz. The average measured noise figure is 6 dB and 1 dB compression point at 3 GHz is ,12 dBm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1879,1881, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23525 [source] On-chip slot antennas in 0.18 ,m CMOS for wireless applicationMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 5 2008Liang Jiang Abstract Two on-chip slot antennas resonating near 30 GHz with different widths (10 and 100 ,m) in standard 0.18 ,m CMOS are presented. S21 between two 10 ,m width slot antennas and between two 100 ,m width ones both with ,3 mm distance through free space is measured. The results indicate that designing on-chip slot antennas with standard CMOS process is feasible, which will support farther improvement of CMOS integration. The slot antennas can be used in compact and low cost transceivers for short range wireless communications. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1187,1191, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23325 [source] A varactorless CMOS direct-injection locked frequency dividerMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2008S.-L. Jang Abstract This paper presents a new integrated direct-injection locked frequency (ILFD) with the capability of quadrature generation. The circuit consists of a quadrature VCO, based on the cross-coupling of two differential LC-tank VCOs and with the coupling transistors placed in parallel with the switch transistors, and two direct injection MOSFETs. No varactors are used, and feedback is applied for frequency tuning. The circuit is implemented using a standard 0.35 ,m CMOS process. Measurement results show that at the supply voltage of 3.3 V, the core power consumption is 27 mW. The free-running ILFD is tunable from 1.5 to 1.98 GHz and the locking range is 2.92,4.26 GHz at 0 dBm. The measured phase noise of free-running ILFD is ,118.3 dBc/Hz while the locked quadrature output phase noise is ,126.7 dBc/Hz at 1 MHz offset frequency from the oscillation frequency of 1.98 GHz, which is 8.4 dB lower than the free running ILFD. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 608,611, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23165 [source] Design of a 3,10 GHz UWB CMOS T/R switchMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 2 2008K.-H Pao Abstract A 3,10 GHz broadband CMOS T/R Switch for ultra-wideband (UWB) transceiver is proposed. This broadband CMOS transmit/receive (T/R) Switch is fabricated based on the 0.18 ,m 1P6M standard CMOS process. On-chip measurement of the CMOS T/R Switch is performed. The insertion loss of the proposed CMOS T/R Switch is about 3.1 ± 1.3 dB. The return losses at both input and output terminals are higher than 14 dB. It is also characterized with 25,34 dB isolation and 18,20 dBm input P1dB. The broadband CMOS T/R Switch shows highly linear phase and group delay of 20 ± 10 ps from 10 MHz to 15 GHz. It can be easily integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 457,460, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23129 [source] A complementary Hartley injection-locked frequency dividerMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 11 2007Sheng-Lyang Jang Abstract This work proposes a new injection-locked frequency divider (ILFD) based on the differential complementary Hartley VCO topology. At the supply voltage of 1.8 V, the tuning range of the free running ILFD is from 7.54 to 7.94 GHz, about 400 MHz, and the locking range of the ILFD is from 14.94 to 16.05 GHz, about 1.11 GHz, at the injection signal power of 0 dBm. The ILFD dissipates 13.54 mW at the supply voltage of 1.8 V and was fabricated in the 1P6M 0.18 ,m CMOS process. The phase noise of the locked ILFD tracks with the low-phase-noise injection source. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2817,2820, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22834 [source] A low voltage highly linear 24-GHz down conversion mixer in 0.18-,m CMOSMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2007Masum Hossain Abstract A K-band low voltage, highly linear folded Gilbert cell mixer in 0.18-,m CMOS is presented. An optimization technique been introduced which is particularly applicable to Gilbert cell type mixers. This technique has been experimentally verified with a down conversion mixer fabricated in a 0.18-,m CMOS process. Utilizing PMOS devices in the transconductance stage and using a 2-V supply voltage, the mixer can down convert from 24 GHz to 10 MHz with an input referred third order intercept of +20 dBm and a conversion gain of 2 dB. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2547,2552, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22759 [source] Sensing with Nafion Coated Carbon Nanotube Field-Effect TransistorsELECTROANALYSIS, Issue 1-2 2004Alexander Star Abstract Sequential CVD and CMOS processes were used to make a FET that has single walled carbon nanotubes to serve as the conducting source to drain channel. This structure can be decorated to provide gas and liquid responses and herein is evaluated as a humdity sensor. The Na+, K+, and Ca2+ ion-exchanged Nafion polymer acts as the chemically sensitive layer in this electrochemical sensor. The effect of gate voltage on the charge-sensitive NT structure was found to be RH dependent over the range of 12,93% RH with msec response time. [source] | |||||||||||||