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Synchronization Scheme (synchronization + scheme)

Distribution by Scientific Domains
Engineering80%

Selected Abstracts

Adaptive synchronization for nonlinear FitzHugh,Nagumo neurons in external electrical stimulation

INTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, Issue 9 2008
Chung-Wen Lai
Abstract This paper investigates the synchronization problem for FitzHugh,Nagumo (FHN) neurons in external electrical stimulations. Using the sliding mode control technique, an adaptive control law is established that guarantees synchronization even when the parameters of the master and slave FHN neurons are fully unknown. A proportional-integral switching surface is introduced to simplify the task of assigning the stability of the closed-loop error system in the sliding mode. Furthermore, the proposed synchronization scheme is then applied to a secure communication system. Computer simulations are provided to verify the effectiveness of the proposed adaptive synchronization scheme. Copyright © 2007 John Wiley & Sons, Ltd. [source]

Some new algebraic criteria for chaos synchronization of Chua's circuits by linear state error feedback control

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 3 2006
Xiaofeng Wu
Abstract The research on the sufficient criterion for chaos synchronization of the master,slave Chua's circuits by linear state error feedback control has received much attention and some synchronization criteria for special control matrix were proposed. In this paper, the above synchronization issue is investigated in the situation of general linear state error feedback controller with propagation delay of control signals from the master Chua's circuit. First of all, a master,slave synchronization scheme for Chua's circuits with propagation delay is given and the relevant error system is derived. Using a quadratic Lyapunov function and frequency domain method, three new algebraic synchronization criteria for the synchronization scheme with general control matrix are proven. They are applied to derive the synchronization criteria for simple control matrices. Some examples are given to show the sharpness of these new criteria compared with the known criteria. Copyright © 2006 John Wiley & Sons, Ltd. [source]

Clock synchronization for packet networks using a weighted least-squares error filtering technique and enabling circuit emulation service

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 6 2007
James Aweya
Abstract Circuit emulation service (CES) allows time-division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase-locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd. [source]

Clock synchronization using a linear process model

INTERNATIONAL JOURNAL OF NETWORK MANAGEMENT, Issue 1 2006
James Aweya
In this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least-squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals. Copyright © 2006 John Wiley & Sons, Ltd. [source]