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Phase-locked Loop (phase-locked + loop)
Selected AbstractsPerformance characterization of a non-linear system as both an adaptive notch filter and a phase-locked loopINTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, Issue 1 2004M. Karimi-Ghartemani Abstract The behaviour of a non-linear dynamical system is described. The system may be characterized as an adaptive notch filter, or alternatively, as a phase-locked loop. Either way, the system has the inherent capability of directly providing estimates of the parameters of the extracted sinusoidal component of its input signal, namely its amplitude, phase and frequency. The structure and mathematical properties of the system are presented for two cases of fixed-frequency and varying-frequency operation. The effects of parameter setting of the system on its performance are studied in detail using computer simulations. Transient and steady-state behaviour of the system are studied in the presence of noise. Simplicity of structure, high noise immunity and robustness and the capability of direct estimation of amplitude, phase and frequency are the salient features of the system when envisaged as an adaptive notch filter or a phase-locked loop. Copyright © 2004 John Wiley & Sons, Ltd. [source] Clock synchronization for packet networks using a weighted least-squares error filtering technique and enabling circuit emulation serviceINTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, Issue 6 2007James Aweya Abstract Circuit emulation service (CES) allows time-division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase-locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd. [source] Mixed H,/H2 design of digital phase-locked loops with polytopic-type uncertaintiesINTERNATIONAL JOURNAL OF ROBUST AND NONLINEAR CONTROL, Issue 14 2002V. Suplin Abstract A robust H, control method is applied to the design of loop filters for digital phase locked loop carrier phase tracking. The proposed method successfully copes with large S -curve slope uncertainty and with a significant decision delay in the closed-loop that may stem from the decoder and/or the equalizer there. The design problem is transformed into a state-feedback control problem where phase and gain-margins should be guaranteed in spite of the uncertainty. Of all the loop filters that achieve the required margins the one that minimizes an upper-bound on the effect of the phase and the measurement noise signals is derived. Copyright © 2002 John Wiley & Sons, Ltd. [source] | ||||||||||