Home About us Contact
|
Home About us Contact | ||
|
|
||
Integrated Circuits (integrate + circuit)
Selected AbstractsMiniaturization of a Laser Doppler Blood Flow Sensor by System-in-Package Technology: Fusion of an Optical Microelectromechanical Systems Chip and Integrated CircuitsIEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 2 2010Wataru Iwasaki Member Abstract We have developed the first and the smallest blood flow sensor composed of integrated circuits (ICs) fused with an optical microelectromechanical systems (MEMS) chip using system-in-package (SiP) technologies for application in a healthcare monitoring system. The probe of this blood flow sensor consists of three layers, and the optical MEMS chip is stacked as the top layer. Through silicon via (TSV), vertical-cavity surface-emitting laser (VCSEL) and cavities enable wafer-level packaging of the optical MEMS chip. The other two layers consisting of ICs are highly densified by SiP technology, and the volume of the probe is miniaturized to about one-sixth of our previously reported integrated laser Doppler blood flowmeter, an MEMS blood flow sensor to which SiP technology was not applied. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source] A coupled FDTD-artificial neural network technique for large-signal analysis of microwave circuitsINTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 1 2002S. Goasguen Abstract We propose a first-order global modeling approach of Monolithic Microwave Integrated Circuits (MMIC) by modeling the active device with a neural network based on a full hydrodynamic model. This neural network describes the nonlinearities of the equivalent circuit parameters of an MESFET implemented in an extended Finite Difference Time Domain mesh to predict large-signal behaviors of the circuits. We successfully represented the transistor characteristics with a one-hidden-layer neural network, whose inputs are the gate voltage Vgs and the drain voltage Vds. The trained neural network shows excellent accuracy and dramatically reduces the computational time in comparison with the hydrodynamic model. Small-signal simulation is performed and validated by comparison with HP-Libra. Then large-signal behaviors are obtained, which demonstrates the successful use of the artificial neural network. © 2002 John Wiley & Sons, Inc. Int J RF and Microwave CAE 12: 25,36, 2002. [source] Identification and authentication of integrated circuitsCONCURRENCY AND COMPUTATION: PRACTICE & EXPERIENCE, Issue 11 2004Blaise Gassend Abstract This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challenge,response protocol. This technique could be used to produce key-cards that are more difficult to clone than ones involving digital keys on the IC. We consider potential venues of attack against our system, and present candidate implementations. Experiments on Field Programmable Gate Arrays show that the technique is viable, but that our current implementations could require some strengthening before it can be considered as secure. Copyright © 2004 John Wiley & Sons, Ltd. [source] Printed Sub-2 V Gel-Electrolyte-Gated Polymer Transistors and CircuitsADVANCED FUNCTIONAL MATERIALS, Issue 4 2010Yu Xia Abstract The fabrication and characterization of printed ion-gel-gated poly(3-hexylthiophene) (P3HT) transistors and integrated circuits is reported, with emphasis on demonstrating both function and performance at supply voltages below 2,V. The key to achieving fast sub-2,V operation is an unusual gel electrolyte based on an ionic liquid and a gelating block copolymer. This gel electrolyte serves as the gate dielectric and has both a short polarization response time (<1,ms) and a large specific capacitance (>10,µF cm,2), which leads simultaneously to high output conductance (>2,mS mm,1), low threshold voltage (<1,V) and high inverter switching frequencies (1,10,kHz). Aerosol-jet-printed inverters, ring oscillators, NAND gates, and flip-flop circuits are demonstrated. The five-stage ring oscillator operates at frequencies up to 150,Hz, corresponding to a propagation delay of 0.7 ms per stage. These printed gel electrolyte gated circuits compare favorably with other reported printed circuits that often require much larger operating voltages. Materials factors influencing the performance of the devices are discussed. [source] Cover Picture: Fabrication of Multicomponent Microsystems by Directed Three-Dimensional Self-Assembly (Adv. Funct.ADVANCED FUNCTIONAL MATERIALS, Issue 5 2005Mater. Abstract Directed three-dimensional self-assembly to assemble and package integrated semiconductor devices is demonstrated by Jacobs and Zheng on p.,732. The self-assembly process uses geometrical shape recognition to identify different components and surface-tension between liquid solder and metal-coated areas to form mechanical and electrical connections. The components (top left) self-assemble in a turbulent flow (center) and form functional multi-component microsystems (bottom right) by sequentially adding parts to the assembly solution. The technique provides, for the first time, a route to enable the realization of three-dimensional heterogeneous microsystems that contain non-identical parts, and connecting them electrically. We have developed a directed self-assembly process for the fabrication of three-dimensional (3D) microsystems that contain non-identical parts and a statistical model that relates the process yield to the process parameters. The self-assembly process uses geometric-shape recognition to identify different components, and surface tension between liquid solder and metal-coated areas to form mechanical and electrical connections. The concept is used to realize self-packaging microsystems that contain non-identical subunits. To enable the realization of microsystems that contain more than two non-identical subunits, sequential self-assembly is introduced, a process that is similar to the formation of heterodimers, heterotrimers, and higher aggregates found in nature, chemistry, and chemical biology. The self-assembly of three-component assemblies is demonstrated by sequentially adding device segments to the assembly solution including two hundred micrometer-sized light-emitting diodes (LEDs) and complementary metal oxide semiconductor (CMOS) integrated circuits. Six hundred AlGaInP/GaAs LED segments self-assembled onto device carriers in two minutes, without defects, and encapsulation units self-assembled onto the LED-carrier assemblies to form a 3D circuit path to operate the final device. The self-assembly process is a well-defined statistical process. The process follows a first-order, non-linear differential equation. The presented model relates the progression of the self-assembly and yield with the process parameters,component population and capture probability,that are defined by the agitation and the component design. [source] Aligned, Ultralong Single-Walled Carbon Nanotubes: From Synthesis, Sorting, to Electronic DevicesADVANCED MATERIALS, Issue 21 2010Zhongfan Liu Abstract Aligned, ultralong single-walled carbon nanotubes (SWNTs) represent attractive building blocks for nanoelectronics. The structural uniformity along their tube axis and well-ordered two-dimensional architectures on wafer surfaces may provide a straightforward platform for fabricating high-performance SWNT-based integrated circuits. On the way towards future nanoelectronic devices, many challenges for such a specific system also exist. This Review summarizes the recent advances in the synthesis, identification and sorting, transfer printing and manipulation, device fabrication and integration of aligned, ultralong SWNTs in detail together with discussion on their major challenges and opportunities for their practical application. [source] Patterning and Templating for NanoelectronicsADVANCED MATERIALS, Issue 6 2010Kosmas Galatsis Abstract The semiconductor industry will soon be launching 32,nm complementary metal oxide semiconductor (CMOS) technology node using 193,nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling. [source] Miniaturization of a Laser Doppler Blood Flow Sensor by System-in-Package Technology: Fusion of an Optical Microelectromechanical Systems Chip and Integrated CircuitsIEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, Issue 2 2010Wataru Iwasaki Member Abstract We have developed the first and the smallest blood flow sensor composed of integrated circuits (ICs) fused with an optical microelectromechanical systems (MEMS) chip using system-in-package (SiP) technologies for application in a healthcare monitoring system. The probe of this blood flow sensor consists of three layers, and the optical MEMS chip is stacked as the top layer. Through silicon via (TSV), vertical-cavity surface-emitting laser (VCSEL) and cavities enable wafer-level packaging of the optical MEMS chip. The other two layers consisting of ICs are highly densified by SiP technology, and the volume of the probe is miniaturized to about one-sixth of our previously reported integrated laser Doppler blood flowmeter, an MEMS blood flow sensor to which SiP technology was not applied. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [source] High-Performance Zinc Oxide Transistors and Circuits Fabricated by Spray Pyrolysis in Ambient AtmosphereADVANCED MATERIALS, Issue 21 2009Aneeqa Bashir The use of a simple deposition technique, namely spray pyrolysis, for the fabrication of high-mobility, low-voltage ZnO transistors and simple integrated circuits is demonstrated. The method is compatible with large-area deposition and could potentially address both the issue of manufacturing cost and high operating voltages. [source] Towards Entire-Carbon-Nanotube Circuits: The Fabrication of Single-Walled-Carbon-Nanotube Field-Effect Transistors with Local Multiwalled-Carbon-Nanotube InterconnectsADVANCED MATERIALS, Issue 13 2009Xuelei Liang Single-walled-carbon-nanotube field-effect transistors with multiwalled carbon nanotubes as local interconnects have been fabricated and integrated into a complementary metal oxide-semiconductor inverter. This device prototype sheds light on future integrated circuits made entirely of carbon nanotubes. [source] Directed Assembly of Polymer Blends Using Nanopatterned TemplatesADVANCED MATERIALS, Issue 7 2009Ming Wei The direct assembly of polymer blends on chemically functionalized surfaces is shown to produce a variety of nonuniform complex patterns. This method provides a powerful tool for easily producing nonuniform patterns in a rapid (30 s), one-step process with high specificity and selectivity for a variety of applications, such as nanolithography, polymeric optoelectronic devices, integrated circuits, and biosensors. [source] Composite right/left handed artificial transmission line structures in CMOS for controlled insertion phase at 30 GHzINTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 2 2009Symon K. Podilchak Abstract Two CMOS integrated circuits are presented that utilize metamaterial composite right/left handed (CRLH) transmission lines (TLs) for zero insertion phase at 30 GHz. Specifically, 2 and 3 unit cell structures are presented with controlled insertion phase that is achieved by cascading lumped element capacitors and spiral inductors in an LC network configuration defining the TL unit cells. Furthermore, the fixed TL structures suggest the possibility of zero, advanced or delayed insertion phases by element variation, or by the use of simple active components. Simulation and measured results are in good agreement with CRLH TL theory, and display a linear insertion phase and flat group delay values that are dependent on the number of unit cells with an insertion loss of ,0.8 dB per cell. These findings suggest that such high speed CRLH TLs structures can be implemented for linear array feeding networks and compact antenna designs in CMOS at millimeter wave frequencies. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [source] From lumped-element circuits to monolithic integrated circuits: A contribution to RF and microwave mixer designINTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, Issue 4 2005Peter Waldow Abstract This article deals with the mixer design for UHF-, microwave- and millimeter-wave applications. Thereby, several aspects such as the chosen technology (lumped elements, hybrid- or monolithic integration) and the applied transmission line (printed circuits, strip-, slot- or coplanar line) are considered. During the course of this contribution, the authors point out the developments in mixer design from lumped-element circuits to monolithic integrated circuits on the example of research activities in Duisburg and Kamp-Lintfort, Germany. The results of these scientific investigations, regarding both the theoretical and experimental aspects, show the feasibility of the proposed techniques. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005. [source] Monitoring roughness and edge shape on semiconductors through multiresolution and multivariate image analysisAICHE JOURNAL, Issue 5 2009Pierantonio Facco Abstract Photolithography is one of the most important processes in the production of integrated circuits. Usually, attentive inspections are required after this process, but are limited to the measurement of some physical parameters such as the critical dimension and the line edge roughness. In this paper, a novel multiresolution multivariate technique is presented to identify the abnormalities on the surface of a photolithographed device and the location of defects in a sensitive fashion by comparing it to a reference optimum, and generating fast, meaningful and reliable information. After analyzing the semiconductor surface image in different levels of resolutions via wavelet decomposition, the application of multivariate statistical monitoring tools allows the in-depth examination of the imprinted features of the product. A two level nested PCA model is used for surface roughness monitoring, while a new strategy based on "spatial moving window" PCA is proposed to analyze the shape of the patterned surface. The effectiveness of the proposed approach is tested in the case of semiconductor surface SEM images after the photolithography process. The approach is general and can be applied also to inspect a product through different types of images, different phases of the same production systems, or different processes. © 2009 American Institute of Chemical Engineers AIChE J, 2009 [source] Crossbar assembly of antibody-functionalized peptide nanotubes via biomimetic molecular recognition,JOURNAL OF PEPTIDE SCIENCE, Issue 2 2008Linglu Yang Abstract Previously, a large scale assembly of nanowires in a parallel array configuration has been demonstrated, and one type of nanowire could interconnect two electrodes in the high-wire density. However, to assemble nanowires into practical logic-gate configurations in integrated circuits, we need more than the parallel assembly of nanowires. For example, when the assembling nanowires are monopolar semiconductors, logic gates such as AND, OR and NOR are to be assembled necessarily from two types of semiconducting nanowires, n -type and p -type, and some of these nanowires must cross perpendicularly to form a crossbar geometry for the logical operation. In this paper, the crossbar assembly of antibody-functionalized peptide nanotubes was demonstrated by a new biomimetic bottom-up technique. Molecular recognition between antigens and antibodies enabled two types of the antibody-functionalized bionanotubes to place them onto targeted locations on substrates, where their complementary antigens were patterned. When two rectangular pads of antigens, human IgG and mouse IgG, were patterned perpendicularly on an Au substrate by nanolithography and then the antihuman IgG nanotubes and the antimouse IgG nanotubes were incubated on this substrate in solution, these bionanotubes were attached onto corresponding locations to form the crossbar configuration. Copyright © 2007 European Peptide Society and John Wiley & Sons, Ltd. [source] A highly integrated Ka-band transceiver module with two channelsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 3 2010Zhigang Wang Abstract A compact Ka-band square-wave modulation transceiver module with two receiving and transmitting channels is presented. This module consists of 15 monolithic microwave integrated circuits, two dielectric resonator oscillators, a E-plane waveguide filter, a coupler, two power dividers, and over 200 components, and works at two Ka-band operating frequency points. The developed Ka-band transceiver module is fabricated using advanced packages techniques, which has a compact size of 120 mm × 60 mm × 20 mm and exhibits greater than 500 mw output power with amplitude imbalance of two output ports less than 30 mw, switch rise time and fall time less than 4 ns, isolation of transmitting two channels more than 63 dB, and voltage standing wave ratio of receiving ports better than 1.3. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 615,618, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25005 [source] An efficient iterative method for analysis of a substrate integrated waveguide structuresMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 1 2010Hassen Zairi Abstract The article presents an efficient method for characterization of substrate integrated waveguide structures. Substrate integrated circuits are considered as an ensemble of conducting vias placed in a parallel-plate waveguide. The analysis is based on the wave concept formulation and the iterative resolution of two relationships between incident and reflected volume-waves. The reflection operator is expressed using Hankel functions and computed by considering the scattering from the ensemble of conducting posts. Numerical results have been obtained for substrate integrated waveguide (SIW) structures already presented in literature. Simulations obtained are compared with recent published results. A good agreement is achieved together with significant improvements both in computational time and memory requirements. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 45,48, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24825 [source] Prediction of radiated EMI from PCB excited by switching noise of ICMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 10 2009Hyun Ho Park Abstract This article describes a methodology to predict radiated emission from the printed circuit boards (PCBs) excited by switching noise of integrated circuits (ICs). Radiation characteristics of PCBs were simulated by using commercial 3D full-wave softwares. IC's switching noise was obtained by measurement. The radiated emission can be calculated by these two factors. To verify the calculation, test PCBs composed of power and ground plane were designed and measured in a 3 m semi-anechoic chamber. The calculated radiated emission showed a good agreement with the measured results. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2262,2266, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24603 [source] Modeling of shielded broadside-coupled substrate striplinesMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 1 2009Sarhan M. Musa Abstract Broadside-coupled substrate striplines represent an essential part of modern integrated circuits. In this article, we will illustrate modeling of inhomogeneous quasi-TEM shielded broadside-coupled substrate striplines using the finite element method (FEM). FEM is especially suitable and effective for the computation of electromagnetic fields in strongly inhomogeneous media. We illustrate that FEM is suitable and effective as other methods for modeling shielded broadside-coupled substrate striplines. We specifically determine the capacitance per unit length, even mode impedance, odd mode impedance, and characteristic impedance of shielded broadside-coupled suspended striplines. Excellent agreement with some results obtained previously is demonstrated. We extended the modeling by designing our own model of shielded broadside-coupled inverted microstrip line and determine the capacitance per unit length, even mode impedance, odd mode impedance, and characteristic impedance. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 9,13, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23960 [source] An alternative analytical reduction scheme in the time-domain layered finite element reduction recovery method for high-frequency IC designMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 9 2008Houle Gan Abstract An alternative analytical reduction scheme was proposed in the time-domain layered finite element reduction recovery (LAFE-RR) method for the analysis of high-frequency integrated circuits. This alternative reduction scheme permits the use of general absorbing boundary conditions in the framework of a time-domain LAFE-RR method. In addition, it allows for an application of the LAFE-RR method to circuit problems in which the system matrices in multiple regions need to be reduced separately. Numerical and experimental results are given to demonstrate its validity. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2337,2341, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23630 [source] Optimization of integrated circuits placement for electric field reduction inside telecommunications equipment using Monte Carlo simulation and parallel recombinative simulated annealingMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 12 2007Sotirios K. Goudos Abstract This article presents a novel approach to the modeling and reduction of electromagnetic interference (EMI) caused by radiated emissions of integrated circuits (ICs) inside rectangular metallic enclosures of telecommunications devices. This type of analysis applies for several types of modern telecommunications equipment found in high-speed networks as well as in mobile communications. A generic model of such a device is created. The ICs are modeled as small electric dipoles and their interaction with the enclosure walls is studied by using the dyadic Green's functions. The electric field on the enclosure walls is computed and its reduction is studied as optimization problem using evolutionary algorithms. Two algorithms are employed: Genetic algorithms (GAs) and parallel recombinative simulated annealing (PRSA). PRSA is a hybrid evolutionary strategy that inherits properties from both GAs and simulated annealing. Monte Carlo simulation is subsequently applied to the optimization results to derive the electric field on the metallic walls and also to perform a worst-case analysis. The applications of the above approach in early PCB design process are discussed. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 3049,3055, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22893 [source] An analysis of layout and temperature effects on magnetic-coupling factor, resistive-coupling factor, and power gain performances of RF transformers for RFIC applicationsMICROWAVE AND OPTICAL TECHNOLOGY LETTERS, Issue 8 2006Yo-Sheng Lin Abstract In this paper, we demonstrate a comprehensive analysis of the temperature effect (from ,25°C to 175°C) on the quality-factors (Q1 and Q2), magnetic-coupling factor (KIm), resistive-coupling factor (KRe), maximum available power gain (GA max), and minimum noise figure (NFmin) performances of RF bifilar and stacked transformers for RFIC applications. Excellent GA max of 0.713 and 0.806 (that is, NFmin of 1.469 and 0.937 dB) were achieved at 5 and 7 GHz, respectively, at room temperature, for a 1:1 stacked transformer mainly due to its high KIm and KRe. In addition, for the 1:1 bifilar transformer at room temperature, though its KIm and KRe are low, good GA max of 0.636 and 0.631 (that is, NFmin of 1.965 and 2.0 dB) were still achieved at 5 and 7 GHz, respectively, mainly due to its high Q1 and Q2. The present analysis is helpful for RF engineers to design temperature-insensitive ultra-low-voltage high-performance transformer-feedback low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs), and other radio-frequency integrated circuits (RF-ICs) which include transformers. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1460,1466, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21732 [source] A unified model incorporating yield, burn-in, and reliabilityNAVAL RESEARCH LOGISTICS: AN INTERNATIONAL JOURNAL, Issue 5 2004Kyungmee O. Kim Abstract The correlated improvement in yield and reliability has been observed in the case studies on integrated circuits and electronic assemblies. This paper presents a model that incorporates yield and reliability with the addition of a burn-in step to explain their correlated improvement. The proposed model includes as special cases several yield and reliability models that have been previously published and thus provides a unifying framework. The model is used to derive a condition for which yield functions can be multiplied to obtain the overall yield. Yield and reliability are compared as a function of operation time, and an analytical condition for burn-in to be effective is also obtained. Finally, Poisson and negative binomial defects models are further considered to investigate how reliability is based on yield. © 2004 Wiley Periodicals, Inc. Naval Research Logistics, 2004. [source] An efficient linear programming solver for optimal filter synthesisNUMERICAL LINEAR ALGEBRA WITH APPLICATIONS, Issue 9 2007Jihong Ren Abstract We consider the problem of l, optimal deconvolution arising in high data-rate communication between integrated circuits. The optimal deconvolver can be found by solving a linear program for which we use Mehrotra's interior-point approach. The critical step is solving the linear system for the normal equations in each iteration. We show that this linear system has a special block structure that can be exploited to obtain a fast solution technique whose overall computational cost depends mostly on the number of design variables, and only linearly on the number of constraints. Numerical experiments validate our findings and illustrate the merits of our approach. Copyright © 2007 John Wiley & Sons, Ltd. [source] Extreme temperature 6H-SiC JFET integrated circuit technologyPHYSICA STATUS SOLIDI (A) APPLICATIONS AND MATERIALS SCIENCE, Issue 10 2009Philip G. Neudeck Abstract Extreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh-environment applications well above the 300 °C effective limit of silicon-on-insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Spectroscopic ellipsometry study of thin diffusion barriers of TaN and Ta for Cu interconnects in integrated circuitsPHYSICA STATUS SOLIDI (A) APPLICATIONS AND MATERIALS SCIENCE, Issue 4 2008S. Rudra Abstract The objective of this work is to study the optical and electrical properties of tantalum nitride and tantalum barrier thin films used against copper diffusion in Si in integrated circuits using spectroscopic ellipsometry in the VUV and UV,visible range. Single layers of tantalum nitride and bilayer films of Ta/TaN were produced by reactive magnetron sputtering on Si(100) substrates covered with a native oxide layer. Ellipsometric measurements were performed in the energy range from 0.73,8.7 eV and the dielectric functions were simulated using Drude,Lorentz model and effective medium approximation (EMA) in order to obtain information regarding film thickness, film composition, free carrier plasma energy, mean relaxation time and electrical resistivity. The film thickness clearly affects the electrical resistivity and the electron mean free path. It was observed that for films of Ta on TaN even after maintaining the deposition condition suitable for the ,-phase of Ta, it turned out to be a mixture of ,- and ,-phases with higher contribution of the ,-phase. It is shown that even a very small intermixture of two different phases of Ta can be determined accurately using ellipsometry. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Application of microsize light-emitting diode structure for monolithic optoelectronic integrated circuitsPHYSICA STATUS SOLIDI (A) APPLICATIONS AND MATERIALS SCIENCE, Issue 6 2007S. Y. Moon Abstract A Si/III,V,N alloys/Si structure was grown on a Si substrate by solid-source molecular beam epitaxy (SSMBE) with an rf plasma nitrogen source and electron-beam (EB) evaporator. A two-dimensional (2D) growth mode was maintained during the growth of all layers. High-resolution X-ray diffraction (HRXRD) revealed that the structure had a small lattice mismatch to the Si substrate. InGaPN/GaPN double-heterostructure (DH) light-emitting diodes (LEDs) were fabricated on Si/III,V,N alloys/Si structure. The various sized LEDs were fabricated to put into the MOSFET for monolithic optoelectronic integrated circuits (OEIC). The luminescence properties of LEDs were evaluated by electroluminescence (EL). A double emission peak from all LED samples was observed at about 642 nm and 695 nm at room temperature (RT). As injection current increased, the emission peak wavelength changed from the peak wavelength of the InGaPN layer to that of the GaPN layer, likely due to carrier overflow of the active layer. A simplified fabrication process for the microsize LED of the unit circuit was proposed. The LEDs with emission areas from 5 × 5 ,m2 to 20 × 20 ,m2 were fabricated. The LED with an emission area of 5 × 5 ,m2 can be applied to an optical device of a monolithic OEIC. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Integrated inductors on porous siliconPHYSICA STATUS SOLIDI (A) APPLICATIONS AND MATERIALS SCIENCE, Issue 5 2007H. Contopanagos The cover picture illustrates the effective use of a thick porous silicon layer as an integrated micro-plate for RF isolation on a silicon substrate, proposed by Harry Contopanagos and Androula Nassiopoulou in their Original Paper [1] in the current issue. What is plotted is the magnitude of the current distribution (colour coded from blue (low) to high (red) values) on the metallization and on a screen 50 µm underneath the bottom oxide layer of a 2-metal integrated CMOS-compatible inductor on bulk silicon (lower right) and on a 50 µm thick porous silicon layer (upper left) for a frequency of 2.5 GHz. Inductors were designed in a standard 0.13 µm CMOS technology. Efficient RF isolation is produced by the porous Si layer, as evidenced by the virtual elimination of surface currents relative to the case of standard CMOS, indicating virtually complete substrate shielding by a 50 µm thick porous Si layer for the relevant size scale. The quality factor of the inductor with the use of the porous Si layer is increased by 100%, reaching a maximum value of 33 for the design shown. The first author of the article is a visiting senior researcher at the Institute of Microelectronics (IMEL), National Center for Scientific Research "Demokritos" (Athens, Greece). His research focuses on electromagnetics and microwave engineering, artificial materials and photonic crystals, wireless front ends, antennas and high-frequency analog integrated circuits. [source] Carbon nanotubes for interconnects in VLSI integrated circuitsPHYSICA STATUS SOLIDI (B) BASIC SOLID STATE PHYSICS, Issue 10 2008J. Robertson Abstract The paper reviews the requirements for carbon nanotubes to be used as interconnects in VLSI integrated circuits. It describes the production by chemical vapour deposition of high density arrays of nanotubes suitable for use as interconnects, and describes their characterisation by Raman and transmission electron microscopy. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] Advanced mHEMT MMICs for 220 GHz high-resolution imaging systemsPHYSICA STATUS SOLIDI (C) - CURRENT TOPICS IN SOLID STATE PHYSICS, Issue 6 2009Sébastien Chartier Abstract The development of advanced millimeter-wave monolithic integrated circuits for application in active and passive high-resolution imaging systems operating beyond 200 GHz is presented. A wideband 210 GHz Low Noise Amplifier has been successfully realized using one of our three metamorphic high electron mobility transistor (mHEMT) technologies in combination with grounded coplanar circuit topology (GCPW). Additionally, a 200 GHz voltage controlled oscillator (VCO) MMIC demonstrating good output power over a wide bandwidth was fabricated, using our 100 nm mHEMT technology. Finally, a high resolution 220 GHz radiometer was realized and shows very promising performance. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [source] | ||||||||||||||||||||||