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Hardware Structures (hardware + structure)
Selected AbstractsAn Approach to Simple Reaction Control for Auto-thermal Fuel-reforming SystemsFUEL CELLS, Issue 4 2004M. Komachiya Abstract A simple approach to reaction control for auto-thermal fuel-reforming systems was proposed and examined. The amount of air supplied to the fuel-reforming system was chosen as the variable in the feedback (closed-loop) control operation, and simply by varying the amount of air supplied, it was attempted to control and stabilize the temperature of the auto-thermal reforming reaction. The amounts of other fuels and water were chosen from pre-determined values by open-loop operation. Since the feedback operation was limited to the air-supply mechanism, it was expected that both the hardware structure of the system and its software configurations could be significantly simplified. The applicability of this simple feedback control operation was confirmed experimentally by using a methanol reformer of the direct-injection type. [source] Increasing data reuse of sparse algebra codes on simultaneous multithreading architecturesCONCURRENCY AND COMPUTATION: PRACTICE & EXPERIENCE, Issue 15 2009J. C. Pichel Abstract In this paper the problem of the locality of sparse algebra codes on simultaneous multithreading (SMT) architectures is studied. In these kind of architectures many hardware structures are dynamically shared among the running threads. This puts a lot of stress on the memory hierarchy, and a poor locality, both inter-thread and intra-thread, may become a major bottleneck in the performance of a code. This behavior is even more pronounced when the code is irregular, which is the case of sparse matrix ones. Therefore, techniques that increase the locality of irregular codes on SMT architectures are important to achieve high performance. This paper proposes a data reordering technique specially tuned for these kind of architectures and codes. It is based on a locality model developed by the authors in previous works. The technique has been tested, first, using a simulator of a SMT architecture, and subsequently, on a real architecture as Intel's Hyper-Threading. Important reductions in the number of cache misses have been achieved, even when the number of running threads grows. When applying the locality improvement technique, we also decrease the total execution time and improve the scalability of the code. Copyright © 2009 John Wiley & Sons, Ltd. [source] CNN applications from the hardware point of view: video sequence segmentationINTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 2-3 2002Asko Kananen Abstract In this paper, the problems present in hardware implementations of cellular non-linear network (CNN) type parallel processors are discussed. Instead of designing a multipurpose processor, or even a full image size application specific parallel processor, we suggest a division of the processing task into categories depending on the cell dynamics and on the spread of the influence of a cell. In this way, drastic savings can be achieved in silicon size and in processing speed. As an example, we use a CNN algorithm that was designed for video image segmentation for object-based compression of video signal. We start with discussion of the problems related to implementation of the algorithm with current multipurpose processors. We then introduce hardware structures that can be used in obtaining certain functionalities. In the same section, we also deal with the division of the processing task. We also compare the introduced hardware solution for the algorithm with multipurpose processor structures in silicon size, power consumption and in processing speed. Copyright © 2002 John Wiley & Sons, Ltd. [source] Embryonic systems implementation with FPGA-based artificial cell network hardware architecturesASIAN JOURNAL OF CONTROL, Issue 2 2010Csaba Szász Abstract The cell-based structure, which makes up the majority of biological organisms, offers the ability to grow with fault-tolerance abilities and self-repair. By adapting these mechanisms and capabilities to nature, scientific approaches have promoted research for understanding related phenomena and associated principles to engine complex novel digital systems and improve their capability. Founded by these observations, the paper is focused on computer-aided modeling, simulation and experimental research of embryonic systems, with the purpose to implement very large scale integrated hardware structures which are able to imitate cells or artificial organism operation mode, with similar robustness and fault-tolerance properties like their biological equivalents from nature. Field Programmable Gate Array (FPGA)-based artificial cell model configuration provided with strongly network communication capabilities is proposed and developed. The presented theoretical and simulation approaches were tested on a laboratory prototype embryonic system (embryonic machine), for study and implementation of basic abilities of living organisms. Copyright © 2010 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society [source] | ||||||||||