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Delay Model (delay + model)

Distribution by Scientific Domains
Engineering100%

Selected Abstracts

End-to-end network delay model for heavy-tailed environments

EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS, Issue 5 2003
David Muñoz-Rodríguez
Adequate quality of Internet Protocol (IP) services demand low transmission delays. However, packets traveling in a network are subject to a variety of delays that degrade severely the quality of service in real-time applications. This paper presents a general packet jitter-assessment methodology for a multi-node path in the presence of heavy-tailed traffic. Using the extreme-value theory, it is shown that delay performance is governed by a proposed networking-processing factor |T|lambda dependent on the traffic characteristics, the processing time along the path segments and the number of nodes in a route. |T|lambda allows the establishment of design constraints and the definition of a feasibility space for a routing algorithm in order to guarantee a quality of service (QoS). Copyright © 2003 AEI. [source]

Filter-based fault detection and diagnosis using output PDFs for stochastic systems with time delays

INTERNATIONAL JOURNAL OF ADAPTIVE CONTROL AND SIGNAL PROCESSING, Issue 4 2006
Y. M. Zhang
Abstract In this paper, a fault detection and diagnosis (FDD) scheme is studied for general stochastic dynamic systems subjected to state time delays. Different from the formulation of classical FDD problems, it is supposed that the measured information for the FDD is the probability density function (PDF) of the system output rather than its actual value. A B-spline expansion technique is applied so that the output PDF can be formulated in terms of the dynamic weights of the B-spline expansion, by which a time delay model can be established between the input and the weights with non-linearities and modelling errors. As a result, the concerned FDD problem can be transformed into a classic FDD problem subject to an uncertain non-linear system with time delays. Feasible criteria to detect the system fault are obtained and a fault diagnosis method is further presented to estimate the fault. Simple simulations are given to demonstrate the efficiency of the proposed approach. Copyright © 2006 John Wiley & Sons, Ltd. [source]

Modelling and design considerations on CML gates under high-current effects

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 6 2005
M. Alioto
Abstract In this paper, the effect of the transit time degradation of bipolar transistors on the power-delay trade-off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high-speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18(9):1369,1375; Model and Design of Bipolar and MOS Current,Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed-form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power-delay trade-off by considering the effect of the transit time degradation in high-speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil-and-paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20-GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd. [source]

Power-delay optimization of D-latch/MUX source coupled logic gates

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Issue 1 2005
M. Alioto
In this paper a design strategy for MUX, XOR and D-latch source coupled logic (SCL) gates is proposed. To this end, an analytical model of the delay and the noise margin as a function of the transistors' aspect ratio and bias current is first introduced. Successively, analytical equations of the transistors' aspect ratio to meet a given noise margin specification are derived as a function of the bias current, and are then used along with the delay model to express the delay as an explicit function of the bias current and noise margin. The simplified delay expression explicitly relates speed performance to power dissipation and the noise margin, thereby providing the designer with the required understanding of the trade-offs involved in the design. Therefore, the criteria proposed allow the designer to consciously manage the power-delay trade-off. The delay dependence on the logic swing is also investigated with results showing that this delay is not necessarily reduced by reducing the logic swing, in contrast with the usual assumption. Since the results obtained are valid for all SCL gates and are independent of the CMOS process used, the guidelines provided afford a deeper understanding of SCL gates from a design point of view. Copyright © 2005 John Wiley & Sons, Ltd. [source]